LAMP: Logic-Circuit Simulators

Abstract

The algorithms used for logic‐circuit simulation in the Logic Analyzer for Maintenance Planning (LAMP) system are described. Several simulators are available to allow a cost‐effective tradeoff between simulation cost and the level of detail needed for a particular application. The true‐value simulator provides efficient simulation of fault‐free logic circuits. Two fault simulators simulate the classical stuck‐at faults as well as shorted‐gate‐output faults. Hyperactive faults, those faults which cause an inordinate amount of simulation activity, are discussed along with their impact on simulation time. A four‐value simulation logic is described which simplifies circuit initialization procedures.

Introduction to D4LASAR, a Test-Generation System

“…However, things do not always go well, in which case there is no substitute for understanding. 4 There is a great deal to learn about modelling problems, and this report does not touch on this aspect. Understanding of work-arounds is important, Test-generation programs use digital computers with their binary processes.…”

STAFAN: An Alternative to Fault Simulation

“…Consider the logic model of the circuit as is often used by simulators [7]. In this model the circuit is described in terms of single-output boolean (AND, OR, NAND, NOR and NOT) gates.…”

Part II: Logic circuit simulation

“…This simulator, as well as the simulators discussed below, are table driven. Bell laboratories has developed the gate-level simulation code LAMP [3]. LAMP is actually a system of codes containing a fault simulator, a logic simulator, and a functional level simulator.…”