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The algorithms used for logic‐circuit simulation in the Logic Analyzer for Maintenance Planning (LAMP) system are described. Several simulators are available to allow a cost‐effective tradeoff between simulation cost and the level of detail needed for a particular application. The true‐value simulator provides efficient simulation of fault‐free logic circuits. Two fault simulators simulate the classical stuck‐at faults as well as shorted‐gate‐output faults. Hyperactive faults, those faults which cause an inordinate amount of simulation activity, are discussed along with their impact on simulation time. A four‐value simulation logic is described which simplifies circuit initialization procedures.