New high-speed bipolar XOR gate with absolutely symmetrical circuit configuration

Schmidt, L.; Rein, H.-M.

doi:10.1049/el:19900279

Cited by 21 publications

(6 citation statements)

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“…However, in order to generate a high-quality signal at twice the input frequency, the delay for both input signals must be the same, a characteristic that the Gilbert multiplier does not possess. To compensate, Schmidt [8] combined two Gilbert cells with inverted signal connections to cancel out the input phase shift.…”

Section: Frequency Multiplier/novel Xor Circuitmentioning

confidence: 99%

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A very wide bandwidth digital VCO using quadrature frequency multiplication and division implemented in AlGaAs/GaAs HBT's

Campbell

Greub

Garg

et al. 1998

IEEE Trans. VLSI Syst.

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Abstract-A digital voltage-controlled oscillator (VCO) is described which uses frequency multiplication and division to achieve very wide bandwidth. The VCO uses current-mode logic and does not require reactive elements such as inductors, capacitors or varactors. A novel, fully symmetric exclusive-OR (XOR) circuit was developed which uses product pairs and emitter-coupled logic. To achieve the highest performance possible, the critical path is symmetric and special physical design techniques were developed to promote matched-capacitance. The maximum measured frequency was 13.66 GHz. The chip occupies 1.9 mm 2 1.6 mm and dissipates 2.45 W at a supply voltage of 06.0 V. With a measured frequency range from 1.25 to 13.66 GHz, this circuit has the widest bandwidth reported in the literature for any VCO, digital or analog.

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Section: Frequency Multiplier/novel Xor Circuitmentioning

confidence: 99%

“…In (8), the phase shift is transferred to the output signal and a DC offset is generated while (11) has a subharmonic component at 2 . Consequently a phase shift on both inputs to one multiplier is preferable to a phase shift on one input of both multipliers, and the arrangement in Fig.…”

Section: Out3 (6)mentioning

confidence: 99%

A very wide bandwidth digital VCO using quadrature frequency multiplication and division implemented in AlGaAs/GaAs HBT's

Campbell

Greub

Garg

et al. 1998

IEEE Trans. VLSI Syst.

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show abstract

“…A more direct solution is to never introduce the problem in the first place by constructing an XOR gate that is absolutely symmetrical. The Symmetrical XOR (SXOR) gate [10] is illustrated in Figure 4.4. 12 Ω.…”

Section: Removal Of Unequal Transit Delaysmentioning

confidence: 99%

Tuning of the Relative Phases of a Rotary Travelling Wave Oscillator

Smith¹

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The work that follows describes the implementation and use of a simple phase detector for phase measurement, and an algorithm to adjust variable Transmission Line (TL) capacitance to tune the phases of an existing RTWO. Symmetrical XOR (SXOR) phase detectors were designed, fabricated in SiGe BiCMOS and tested to resolve 1 • of phase error over 45 • ± 10 • and 90 • ± 10 • up to 12 GHz. These phase detectors were used to measure and calibrate the phase of 45 • transmission line sections of an 18-GHz RTWO fabricated in SiGe BiCMOS. This phase tuning was carried out by a simple phase alignment algorithm that can be implemented easily in verilog. This RTWO phase tuning system was shown to function correctly in simulation. Although the fabricated version did not converge correctly, the algorithm was able to adjust the phase of RTWO TL sections. The circuit problem preventing convergence is understood and can be corrected.

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“…In phase detector design, this amount of error will be very crucial because it will cause the wrong phase difference to be detected by the PD. In order to alleviate the small phase error, an absolutely symmetrical XOR gate in MCML circuit technique is utilized [42]. The circuit schematic is shown in Consequently, the delay time differences between A to Q and B to Q are exactly compensated, and the slight phase error can be minimized.…”

Section: Xor Gatementioning

confidence: 99%

“…As it can be observed from Figure 5.6, the obvious disadvantage of the absolutely symmetrical XOR gate is the larger input capacitance, compared to common XOR gate in Figure 5.5. However, this drawback can be mitigated, because (at a given internal output swing and load resistance) each internal gate requires only half of the current of a standard gate [42]. As a consequence, the size of differential pair transistors can be considerably reduced, resulting in a reduction of the input capacitance.…”

Section: Xor Gatementioning

confidence: 99%

Design of a low-voltage low-power CMOS phase detector for SONET/SDH standards

Wu¹

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Due to the exponential growth in the Internet data traffic, the volume of data over the telecommunications network has increased rapidly. The required capacity of the transport (transmission) links must also increase, motivating work on faster communication channels. Among all the available transmission media, optical fiber achieves highest bandwidth with the lowest loss. Thus, the development of telecommunication transport networks has been accelerated, resulting in the Synchronous Optical Network (SONET)/Synchronous Digital Hierarchy (SDH) standards. The SONET OC-192, a standard for 10-Gb/s serial links, has been well established. The clock and data recovery (CDR) circuit is the most challenging part of building a optical receiver for the SONET OC-192 standard because of the highspeed operation and the random input data stream. Further, the CDR must comply with stringent jitter requirements specified in the standard. The phase detector, being the first stage dealing with incoming high-speed data, is a crucial building block of a CDR circuit. Its characteristics determine the design styles of other block elements in a CDR circuit as well as the entire performance of CDR system critically. In this project, a new non-sequential linear high-speed phase detector (PD) for SONET OC-192 standard is proposed. The 0.18^im CMOS Analog/RF process of Chartered Semiconductor Manufacturing Ltd (CSM) is used throughout the design. The data rate is set to be 10-Gb/s according to the standard. The proposed I

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New high-speed bipolar XOR gate with absolutely symmetrical circuit configuration

Cited by 21 publications

References 0 publications

A very wide bandwidth digital VCO using quadrature frequency multiplication and division implemented in AlGaAs/GaAs HBT's

A very wide bandwidth digital VCO using quadrature frequency multiplication and division implemented in AlGaAs/GaAs HBT's

Tuning of the Relative Phases of a Rotary Travelling Wave Oscillator

Design of a low-voltage low-power CMOS phase detector for SONET/SDH standards

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