<i>N</i> Point DCT VLSI Architecture for Emerging HEVC Standard

Ahmed, Ashfaq; Shahid, Muhammad; Rehman, Ata Ur

doi:10.1155/2012/752024

Cited by 43 publications

(32 citation statements)

References 22 publications

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“…Moreover, the proposed architecture can be pruned to reduce the complexity of implementation substantially with only a marginal effect on the coding performance for both folded and full-parallel 2-D DCT-II implementations. Ahmed et al [21] have proposed a dynamic N-point DCT-II for HEVC inverse transform of sizes 4x4, 8x8, 16x16 and 32x32. The hardware architecture is partially folded in order to save the area and improve the speed up of the design.…”

Section: B Hardware Transform Implementationmentioning

confidence: 99%

Hardware Design and Implementation of Adaptive Multiple Transforms for the Versatile Video Coding Standard

Kammoun

Hamidouche

Belghith

et al. 2018

IEEE Trans. Consumer Electron.

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Section: B Hardware Transform Implementationmentioning

confidence: 99%

Hardware Design and Implementation of Adaptive Multiple Transforms for the Versatile Video Coding Standard

Kammoun

Hamidouche

Belghith

et al. 2018

IEEE Trans. Consumer Electron.

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“…Even though it uses a smaller technology compared to SDCT (45 nm vs. 65 nm) that grants a faster clock frequency (1.7×), the SDCT presents 4.7× higher throughput. Ahmed et al [17] designed a folded structure that decomposes the DCT matrices into sparse submatrices to reduce the multiplications. Moreover, these last are eliminated thanks to a lifting scheme.…”

Section: Comparison With Previous Workmentioning

confidence: 99%

Steerable-Discrete-Cosine-Transform (SDCT): Hardware Implementation and Performance Analysis

Peloso

Capra

Sole

et al. 2020

Sensors

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In the last years, the need for new efficient video compression methods grown rapidly as frame resolution has increased dramatically. The Joint Collaborative Team on Video Coding (JCT-VC) effort produced in 2013 the H.265/High Efficiency Video Coding (HEVC) standard, which represents the state of the art in video coding standards. Nevertheless, in the last years, new algorithms and techniques to improve coding efficiency have been proposed. One promising approach relies on embedding direction capabilities into the transform stage. Recently, the Steerable Discrete Cosine Transform (SDCT) has been proposed to exploit directional DCT using a basis having different orientation angles. The SDCT leads to a sparser representation, which translates to improved coding efficiency. Preliminary results show that the SDCT can be embedded into the HEVC standard, providing better compression ratios. This paper presents a hardware architecture for the SDCT, which is able to work at a frequency of 188 M Hz , reaching a throughput of 3.00 GSample/s. In particular, this architecture supports 8k UltraHigh Definition (UHD) (7680 × 4320) with a frame rate of 60 Hz , which is one of the best resolutions supported by HEVC.

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“…With the factorization relationship of DCT, the number of arithmetic operations of transform can be reduced. Ahmed et al [9] decomposed the DCT matrix into sparse submatrices where the multiplications are avoided by using the lifting scheme. Arai et al [10] proposed AAN fast algorithm based on common factor extraction algorithm in which the complicated common factors were moved from transform kernel to scale part.…”

Section: Introductionmentioning

confidence: 99%

A Bit-Plane Decomposition Matrix-Based VLSI Integer Transform Architecture for HEVC

Huang

Gao

2017

IEEE Trans. Circuits Syst. II

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In this paper, a new VLSI integer transform architecture is proposed for high efficient video coding (HEVC) encoder. The architecture is designed based on the signed bitplane transform (SBT) matrices which are derived from the bitplane decompositions of the integer transform matrices in HEVC. Mathematically, an integer transform matrix can be equally expressed by the binary weighted sum of several SBT matrices which are only composed of binary 0 or ±1. The SBT matrices are very simple and have lower bitwidth than the original integer transform in the form. The SBT matrices are also sparse in which there are many zero elements. The sparse characteristic of SBT matrices is very helpful for saving the addition operators of SBT. In the proposed architecture, instead of the original integer transform in high bitwidth, the video data can be respectively transformed with the SBT matrices in lower bitwidth. As the result, the delay of transform unit circuit can be significantly reduced with the proposed SBT. Moreover, exploiting the redundant element characteristic of SBT matrices, in which the elements are 0 or ±1, the adder reuse strategy is proposed for our transform architecture, which can save the circuit area efficiently. The simulation results show that, employing the proposed strategies, the VLSI transform architecture can be synthesized in a proper area with a high working frequency and low latency. The architecture can support all HEVC encoders coding Ultra HD video sequences in real time.

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N Point DCT VLSI Architecture for Emerging HEVC Standard

Cited by 43 publications

References 22 publications

Hardware Design and Implementation of Adaptive Multiple Transforms for the Versatile Video Coding Standard

Hardware Design and Implementation of Adaptive Multiple Transforms for the Versatile Video Coding Standard

Steerable-Discrete-Cosine-Transform (SDCT): Hardware Implementation and Performance Analysis

A Bit-Plane Decomposition Matrix-Based VLSI Integer Transform Architecture for HEVC

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