IBM Memory Expansion Technology (MXT)

Abstract

Several technologies are leveraged to establish an architecture for a low-cost, highperformance memory controller and memory system that more than double the effective size of the installed main memory without significant added cost. This architecture is the first of its kind to employ real-time main-memory content compression at a performance competitive with the best the market has to offer. A large low-latency shared cache exists between the processor bus and a content-compressed main memory. Highspeed, low-latency hardware performs realtime compression and decompression of data traffic between the shared cache and the main memory. Sophisticated memory management hardware dynamically allocates main-memory storage in small sectors to accommodate storing the variable-sized compressed data without the need for "garbage" collection or significant wasted space due to fragmentation. Though the main-memory compression ratio is limited to the range 1:1-64:1, typical ratios range between 2:1 and 6:1, as measured in "real-world" system applications. Architecture Conventional "commodity" computer systems typically share a common architecture, in which a collection of processors are connected to a common SDRAM-based

Design and Implementation of a High-Performance Microprocessor Cache Compression Algorithm

“…We first present the performance, power consumption, and area overheads of the compression/decompression hardware when synthesized for integration within a microprocessor. Then, we compare the compression ratio and performance of C-Pack to other algorithms considered for cache compression: MXT [4], Xmatch [14], and FPC [5]. Finally, we describe the implications of our findings on the feasibility of using C-Pack based cache compression within a microprocessor.…”

“…A number of researchers have assumed the use of general-purpose main memory compression hardware, e.g., MXT [4], for on-chip cache compression. Although appropriate for compressing main memory, such hardware has performance, area, or power consumption costs that contradict its use in cache compression.…”

Lazy Management for Frequency Table on Hardware-Based Stream Lossless Data Compression

“…Initially, they looked into the main memory using the software LZ-based compression method [22]. Similarly, IBM (North Castle Armonk, NY, USA) has released a memory system called MXT [23], based on hardware implementation using the adaptive LZ-based compression. It reduces the memory usage than the actual data size.…”

High-performance operating system controlled memory compression

“…Main memory compression techniques [3] insert a hardware compression/decompression unit between cache and RAM. Data is stored uncompressed in cache, and compressed on-the-fly when transferred to memory.…”

“…IBM's MXT technology [3] used a hardware parallelized derivative of LZ77 [2]. Kjelso, et al [9] designed X-Match, a hardwarebased dictionary coding algorithm.…”