IBM S/390 Parallel Enterprise Server G5 fault tolerance: A historical perspective

Spainhower, Lisa; Gregg, T. A.

doi:10.1147/rd.435.0863

Cited by 154 publications

(86 citation statements)

References 13 publications

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“…The most effective method of dealing with soft errors in memory components is to use codes like parity, or ECC [33]. Execution redundancy is a widely used technique to detect errors in the logic, either using the multithreading capabilities [34,43] or hardware redundancy [45,46]. DIVA [3] uses a simple in-order core as a checker for an out-of-order core.…”

Section: Related Workmentioning

confidence: 99%

Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery

Upasani

Vera

González

2014

SIGARCH Comput. Archit. News

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Section: Related Workmentioning

confidence: 99%

Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery

Upasani

Vera

González

2014

SIGARCH Comput. Archit. News

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“…In a reconfigurable architecture, recovery entails isolating defective module(s) and incorporating spare structures as needed. Support for reconfiguration can be achieved at various granularities, from ultrafine grain systems [7,8] that have the ability to replace individual logic gates to coarser designs that focus on isolating entire processor cores [1,2,[9][10][11][12][13][14]21]. This choice presents a trade-off between complexity of implementation and potential lifetime enhancement [15,16].…”

Section: Related Workmentioning

confidence: 99%

Hierarchical Multiplexing Interconnection Structure for Fault-Tolerant Reconfigurable Chip Multiprocessor

Kim

2011

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Stage-level reconfigurable chip multiprocessor (CMP) aims to achieve highly reliable and fault tolerant computing by using interwoven pipeline stages and on-chip interconnect for communicating with each other. The existing crossbar-switch based stage-level reconfigurable CMPs offer high reliability at the cost of significant area/power overheads. These overheads make realizing large CMPs prohibitive due to the area and power consumed by heavy interconnection networks. On other hand, area/ power-efficient architectures offer less reliability and inefficient stage-level resource utilization. In this paper, I propose a hierarchical multiplexing interconnection structure in lieu of crossbar interconnect to design area/power-efficient stage-level reconfigurable CMP. The proposed approach is able to keep the reliability offered by the crossbar-switch while reducing the area and power overheads. Experimental results show that the proposed approach reduces area by up to 21% and power by up to 32% when compared with the crossbar-switch based interconnection network.

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“…Duplicate and compare is an old and effective strategy for hardware error detection [14]. The same input is sent to identical components and the outputs from the components are compared.…”

Section: Detection By Comparison Of Outputs From Diverse Softwarementioning

confidence: 99%

On-Line Intrusion Protection by Detecting Attacks with Diversity

Reynolds¹,

Just²,

Lawson³

et al. 2003

Research Directions in Data and Applications Security

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We have built a system for protecting web servers to securely connected, known users that includes an innovative use of diversity for on-line attack identification. We are able to use attack identification to immediately protect the system without debilitating waits for anti-virus updates or software patches by positively verifying attacks with a sandbox. Unique to our approach is the use of diverse process pairs not only for isolation benefits but also for detection. The architecture uses the comparison of outputs from diverse applications to provide a significant and novel intrusion detection capability. With this technique, we gain the benefits of n-version programming without its controversial disadvantages. Diversity of applications also contributes to the isolation of intrusions by software, which is further improved by random rejuvenation.

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IBM S/390 Parallel Enterprise Server G5 fault tolerance: A historical perspective

Cited by 154 publications

References 13 publications

Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery

Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery

Hierarchical Multiplexing Interconnection Structure for Fault-Tolerant Reconfigurable Chip Multiprocessor

On-Line Intrusion Protection by Detecting Attacks with Diversity

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