IBM’s Next Generation POWER Processor

Stuecheli, Jeff; Willenborg, Scott; Starke, William J.

doi:10.1109/hotchips.2019.8875663

Cited by 6 publications

(2 citation statements)

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“…Similarly to a write, a PIM request instruction requires two registers as input: address and data. 3 IBM's Power9 has 16 OpenCAPI channels [73].…”

Section: System Configurationmentioning

confidence: 99%

PIMDB: Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics

Perach¹,

Ronen²,

Kimelfeld³

et al. 2022

Preprint

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Bulk-bitwise processing-in-memory (PIM), where large bitwise operations are performed in parallel by the memory array itself, is an emerging form of computation with the potential to mitigate the memory wall problem. This paper examines the capabilities of bulk-bitwise PIM by constructing PIMDB, a fully-digital system based on memristive stateful logic, utilizing and focusing on in-memory bulk-bitwise operations, designed to accelerate a real-life workload: analytical processing of relational databases. We introduce a host processor programming model to support bulk-bitwise PIM in virtual memory, develop techniques to efficiently perform in-memory filtering and aggregation operations, and present the mapping of the application into the memory. When tested against an equivalent in-memory database on the same host system, our approach substantially lowers the number of required memory read operations, thus accelerating TPC-H filter operations by 1.6×-18× and full queries by 56×-608×, while reducing the energy consumption by 1.7×-18.6× and 0.81×-12× for these benchmarks, respectively. Our extensive evaluation uses the gem5 full-system simulation environment.

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“…Similarly to a write, a PIM request instruction requires two registers as input: address and data. 3 IBM's Power9 has 16 OpenCAPI channels [73].…”

Section: System Configurationmentioning

confidence: 99%

PIMDB: Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics

Perach¹,

Ronen²,

Kimelfeld³

et al. 2022

Preprint

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“…The recent advances in die-stacked and in-package embedded DRAM technologies have motivated the industry to explore DRAM caches as a viable option for designing very large last-level caches [Arroyo et al 2011;IBM 2012;Intel 2013;Stuecheli 2013;Kurd et al 2014]. Recent research studies exploring the architecture of the DRAM caches have focused on traditional cache organizations with fine-grain (e.g., 64 or 128 bytes) [Loh and Hill 2011;Meza et al 2012;Qureshi and Loh 2012;Sim et al 7:2 M. Chaudhuri et al 2012; El-Nacouzi et al 2013;Hameed et al 2013], coarse-grain (e.g., 512 bytes to 4KB) [Jiang et al 2010;Jevdjic et al 2013Jevdjic et al , 2014Lee et al 2015;Jang et al 2016], or mixed-grain [Gulur et al 2014] allocation units (referred to as the DRAM cache block size).…”

Section: Introductionmentioning

confidence: 99%

Micro-Sector Cache

Chaudhuri

Agrawal

Gaur

et al. 2017

ACM Trans. Archit. Code Optim.

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Recent research proposals on DRAM caches with conventional allocation units (64 or 128 bytes) as well as large allocation units (512 bytes to 4KB) have explored ways to minimize the space/latency impact of the tag store and maximize the effective utilization of the bandwidth. In this article, we study sectored DRAM caches that exercise large allocation units called sectors, invest reasonably small storage to maintain tag/state, enable space-and bandwidth-efficient tag/state caching due to low tag working set size and large data coverage per tag element, and minimize main memory bandwidth wastage by fetching only the useful portions of an allocated sector. However, the sectored caches suffer from poor space utilization, since a large sector is always allocated even if the sector utilization is low. The recently proposed Unison cache addresses only a special case of this problem by not allocating the sectors that have only one active block. We propose Micro-sector cache, a locality-aware sectored DRAM cache architecture that features a flexible mechanism to allocate cache blocks within a sector and a locality-aware sector replacement algorithm. Simulation studies on a set of 30 16-way multi-programmed workloads show that our proposal, when incorporated in an optimized Unison cache baseline, improves performance (weighted speedup) by 8%, 14%, and 16% on average, respectively, for 1KB, 2KB, and 4KB sectors at 128MB capacity. These performance improvements result from significantly better cache space utilization, leading to 18%, 21%, and 22% average reduction in DRAM cache read misses, respectively, for 1KB, 2KB, and 4KB sectors at 128MB capacity. We evaluate our proposal for DRAM cache capacities ranging from 128MB to 1GB.

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Trends in computing technologies and markets: The HEPiX TechWatch WG

et al. 2020

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Driven by the need to carefully plan and optimise the resources for the next data taking periods of Big Science projects, such as CERN’s Large Hadron Collider and others, sites started a common activity, the HEPiX Technology Watch Working Group, tasked with tracking the evolution of technologies and markets of concern to the data centres. The talk will give an overview of general and semiconductor markets, server markets, CPUs and accelerators, memories, storage and networks; it will highlight important areas of uncertainties and risks.

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IBM’s Next Generation POWER Processor

Cited by 6 publications

References 0 publications

PIMDB: Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics

PIMDB: Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics

Micro-Sector Cache

Trends in computing technologies and markets: The HEPiX TechWatch WG

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