IBM System z10 performance improvements with software and hardware synergy

Jackson, Kenneth R.; Wisniewski, Mark; Schmidt, Douglas C.; Hild, U.; Heisig, Stephen; Yeh, P.; Gellerich, Wolfgang

doi:10.1147/jrd.2009.5388576

Cited by 5 publications

(3 citation statements)

References 4 publications

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“…Performance-counter data generated by the hardware [12] is added to the control-flow-graph representation of the program created by the compiler to produce the input for the mining tool. The Testarossa compiler comes equipped with a rich set of logging features, including the ability to report all generated machine instructions.…”

Section: Preparation Of Data For Miningmentioning

confidence: 99%

Mining Opportunities for Code Improvement in a Just-In-Time Compiler

Jocksch

Mitran

Siu

et al. 2010

Lecture Notes in Computer Science

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Abstract. The productivity of a compiler development team depends on its ability not only to the design effective solutions to known code generation problems, but also to uncover potential code improvement opportunities. This paper describes a data mining tool that can be used to identify such opportunities based on a combination of hardware-profiling data and on compiler-generated counters. This data is combined into an Execution Flow Graph (EFG) and then FlowGSP, a new data mining algorithm, finds sequences of attributes associated with subpaths of the EFG. Many examples of important opportunities for code improvement in the IBM R Testarossa compiler are described to illustrate the usefulness of this data mining technique. This mining tool is specially useful for programs whose execution is not dominated by a small set of frequently executed loops. Information about the amount of space and time required to run the mining tool are also provided. In comparison with manual search through the data, the mining tool saved a significant amount of compiler development time and effort.

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Section: Preparation Of Data For Miningmentioning

confidence: 99%

Mining Opportunities for Code Improvement in a Just-In-Time Compiler

Jocksch

Mitran

Siu

et al. 2010

Lecture Notes in Computer Science

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“…These instructions are implemented as nonblocking to avoid unnecessary pipeline rejects and delays. For more software optimization insights, see Reference [10].…”

Section: Storage Accessesmentioning

confidence: 99%

Design and microarchitecture of the IBM System z10 microprocessor

Shum¹,

Busaba²,

Dao-Trong

et al. 2009

IBM J. Res. & Dev.

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The IBM System z10e microprocessor is currently the fastest running 64-bit CISC (complex instruction set computer) microprocessor. This microprocessor operates at 4.4 GHz and provides up to two times performance improvement compared with its predecessor, the System z9t microprocessor. In addition to its ultrahigh-frequency pipeline, the z10e microprocessor offers such performance enhancements as a sophisticated branch-prediction structure, a large second-level private cache, a data-prefetch engine, and a hardwired decimal floating-point arithmetic unit. The z10 microprocessor also implements new architectural features that allow better software optimization across compiled applications. These features include new instructions that help shorten the code path lengths and new facilities for software-directed cache management and the use of 1-MB virtual pages. The innovative microarchitecture of the z10 microprocessor and notable differences from its predecessors and the IBM POWER6e microprocessor are discussed.

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“…We identified that <L, L, L> is prevalent in most workloads running on top of IBM z10 eServer mainframe [13] . Our experiment shows 4% of total data cache misses and 2.6% of total pipeline stalls are observed as caused by this pattern, which explains the significant portion of execution time (accounting for up to 1.9% of total ticks) eaten by the pattern.…”

Section: Introductionmentioning

confidence: 99%

Frequent Instruction Sequential Pattern Mining in Hardware Sample Data

Zou

Xiao

Hou

et al. 2010

2010 IEEE International Conference on Data Mining

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When parallelism and heterogeneity has become the trend for computer system design, both the size and the complexity of the hardware sample data generated by Performance Monitoring Unit (PMU) increase fast, thus automatic analysis methods, i.e. data mining methods, are urgently needed to accelerate hardware sample data analysis. We are the first to study instruction sequential pattern mining for hardware sample data. It is a challenging task due to the implicit sequential relationship contained in the data and due to the importance of low frequency patterns. As a solution, we i) provide a novel algorithm ProfSpan; ii) adapt two existing algorithms, which are based on candidate generation and projected database generation, to hardware sample data. Our evaluation results show ProfSpan can reduce up to 75% and 80% of execution time compared with other two algorithms. Particularly, up to 50% of frequent patterns mined by ProfSpan in hardware sample data are crossing basic block boundaries and can not be found by existing methods for source code or disassembly code. We also analyze three example patterns identified by ProfSpan: consecutive loads, JIT entry sequence, and conditional code dependency sequence, to illustrate how ProfSpan can benefit performance analysis. Finally, we apply patterns to module classification and obtain promising results.

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IBM System z10 performance improvements with software and hardware synergy

Cited by 5 publications

References 4 publications

Mining Opportunities for Code Improvement in a Just-In-Time Compiler

Mining Opportunities for Code Improvement in a Just-In-Time Compiler

Design and microarchitecture of the IBM System z10 microprocessor

Frequent Instruction Sequential Pattern Mining in Hardware Sample Data

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