IC laser trimming speed-up through wafer-level spatial correlation modeling

Xanthopoulos, Constantinos; Huang, Ke; Poonawala, Abbas; Nahar, Amit; Orr, Bob; Carulli, John M.; Makris, Yiorgos

doi:10.1109/test.2014.7035329

Cited by 6 publications

(3 citation statements)

References 13 publications

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“…Such methods can be differentiated as static and dynamic ones. Static calibration methods are represented mainly by trimming, where laser or current blown fuses are used [28]. Dynamic calibration methods include, for example, the chopper stabilization [29], auto-zeroing [30] or digital calibration [31].…”

Section: Calibration Techniquesmentioning

confidence: 99%

Ultra-Low Voltage Analog IC Design: Challenges, Methods and Examples

Stopjaková¹,

Rakús²,

Kovac³

et al. 2018

RADIOENGINEERING

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The paper brings an overview of main challenges and design techniques effectively applicable for ultra-low voltage analog integrated circuits in nanoscale technologies. New design challenges linked with a low value of the supply voltage and the process fluctuation in nanotechnologies, such as device models, robustness to process variation, device mismatch and others are discussed firstly. Then, design techniques and approaches to analog integrated circuits towards (ultra) low-voltage systems and applications are described. Finally, examples of basic building blocks of ultra-low voltage analog ICs designed in standard CMOS technology using such design techniques are presented. Finally, the developed circuits are compared to the state-of-the-art solutions in terms of the main parameters and features.

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Section: Calibration Techniquesmentioning

confidence: 99%

Ultra-Low Voltage Analog IC Design: Challenges, Methods and Examples

Stopjaková¹,

Rakús²,

Kovac³

et al. 2018

RADIOENGINEERING

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“…A representative description of calibration methods for performance improvement can be found in [3] and [4]. Different techniques for trim optimizations are proposed in [5] and [6]. These involve optimizations for search of one trim code within the DUT and as well as across DUTs.…”

Section: Introductionmentioning

confidence: 99%

“…[5] focuses on the former, using smarter search methods, onchip measurement and parallelism. [6] focuses on the latter, using wafer level spatial correlation and verniered (coarse and fine) trims across neighboring dies. However, there are no specific methods reported in the literature which optimize trims for interdependent parameters.…”

Section: Introductionmentioning

confidence: 99%

A novel technique for interdependent trim code optimization

Bongale

Sundaresan²,

Ghosh

et al. 2016

2016 IEEE 34th VLSI Test Symposium (VTS)

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As integrated circuits become increasingly complex, the fabrication process renders them more marginal to specification parameters. Consequently, these circuits have to be tuned post fabrication to compensate for process marginality and thereby optimize their performance as well as to improve yields. This process of tuning is commonly termed as trimming, wherein the right set of digital trim codes is identified and used as a calibration setting by writing these codes into the hardware configuration registers. This paper addresses the problem of carrying out multi-variable trims involving two or more parameters, codes for which must be simultaneously searched and set, in order to attain the desired performance of the circuit. A novel low-cost hardware implementation of the Simplex minimization algorithm with speed-up improvements is described. This implementation is amenable for on-chip BIST (built-in self-test) and can also be directly implemented as part of the ATE (automatic test equipment) program. Experimental results are presented on two industrial circuits. Improvements in terms of trim code search time and attaining better performance are shown.

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Machine learning applications in IC testing

Stratigopoulos

2018

2018 IEEE 23rd European Test Symposium (ETS)

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IC laser trimming speed-up through wafer-level spatial correlation modeling

Cited by 6 publications

References 13 publications

Ultra-Low Voltage Analog IC Design: Challenges, Methods and Examples

Ultra-Low Voltage Analog IC Design: Challenges, Methods and Examples

A novel technique for interdependent trim code optimization

Machine learning applications in IC testing

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