Ultra-Low Voltage Analog IC Design: Challenges, Methods and Examples

Abstract

The paper brings an overview of main challenges and design techniques effectively applicable for ultra-low voltage analog integrated circuits in nanoscale technologies. New design challenges linked with a low value of the supply voltage and the process fluctuation in nanotechnologies, such as device models, robustness to process variation, device mismatch and others are discussed firstly. Then, design techniques and approaches to analog integrated circuits towards (ultra) low-voltage systems and applications are described. Finally, examples of basic building blocks of ultra-low voltage analog ICs designed in standard CMOS technology using such design techniques are presented. Finally, the developed circuits are compared to the state-of-the-art solutions in terms of the main parameters and features.

Optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation

“…The comparator passes all 45 process corner in clock frequency 2MHz. As shown in Figure 6, the proposed design able to operate in For process corner (FS;720mV;0°C), failure occurred in test sequence number (3,6,8,9,11). The failure occurred in minimum positive input INP is 400.4mV.…”

“…During this time, a voltage different at node fm and fp is developed and it becomes a gain to the latch state. This topology has less kickback noise due to the isolation between input and output node [1][2][3][4][5][6][7][8][9][10]. However, this topology consumes high power because of pre-amp and latching stage start to operate at the same duration .…”

“…For (SS;800mV;0°C) process corner, the failure occurred at test sequence number (3,6,8,9). The failure occurred in minimum positive input INP is 400.4mV.…”

“…To ensure the robustness of a design, process corner simulation is required at the design stage. Process corner represents the extremes parameter variation of integrated circuit design which is fabricated on semiconductor wafer [6][7][8][9][10][11][12][13][14][15]. Parameter variations include range of process transistor properties, supply voltages and die temperatures [8,9].…”

“…The most popular energy efficient comparator is dynamic comparator Figure 1 which only operates during regeneration time [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18]. The additional features are high input impedance, rail to rail output swing, zero static power, low offset voltage and fast decision making that comes from strong positive feedback and .…”