IDDQ and AC scan: the war against unmodelled defects

Maxwell, Peter; Aitken, Rob; Kollitz, K.R.; Brown, Alastair

doi:10.1109/test.1996.556969

Cited by 131 publications

(51 citation statements)

References 18 publications

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“…Currently, scan testing for the stuck-at fault model [1], [2] is one of the most popular test methods for VLSIs. However, it has been reported that scan testing for the stuck-at fault model may not detect defective VLSIs [3], and that delay testing and at-speed functional testing can effectively improve test quality [4]. Scan testing is based on the structure of the circuit rather than its function and the test pattern can be generated with this method.…”

Section: Introductionmentioning

confidence: 99%

A Fault Dependent Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint

Inoue

Hosokawa

Fujiwara

2010

IEICE Trans. Inf. & Syst.

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SUMMARYSince scan testing is not based on the function of the circuit, but rather the structure, it is considered to be both a form of over testing and under testing. Moreover, it is important to test VLSIs using the given function. Since the functional specifications are described explicitly in the FSMs, high test quality is expected by performing logical fault testing and timing fault testing. This paper proposes a fault-dependent test generation method to detect specified fault models completely and to increase defect coverage as much as possible under the test length constraint. We present experimental results for MCNC'91 benchmark circuits to evaluate bridging fault coverage, transition fault coverage, and statistical delay quality level and to show the effectiveness of the proposed test generation method compared with a stuck-at fault-dependent test generation method.

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Section: Introductionmentioning

confidence: 99%

A Fault Dependent Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint

Inoue

Hosokawa

Fujiwara

2010

IEICE Trans. Inf. & Syst.

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“…Even faults that remain undiscovered using functional testing based on fault models are detected by IDDQ measurements [1].…”

Section: Introductionmentioning

confidence: 99%

Deterministic Algorithms for ATPG under Leakage Constraints

Fey

2009

2009 Asian Test Symposium

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Abstract-Measuring the steady state leakage current (IDDQ) is very successful in detecting faults not discovered by standard fault models. But vector dependencies of IDDQ decrease the resolution.We propose deterministic ATPG algorithms to create test vectors within predefined leakage ranges. Even when random pattern generation does not find test vectors, the proposed algorithms identify vectors within the desired range. Experimental results confirm that leakage constraints are effectively handled during test pattern generation without decreasing fault coverage.Keywords-Algorithms, deterministic ATPG, IDDQ I. INTRODUCTIONThe steady state leakage current (IDDQ) is a good indicator to decide whether a circuit contains failures introduced during production. Even faults that remain undiscovered using functional testing based on fault models are detected by IDDQ measurements [1].With continuously shrinking feature sizes the IDDQ current of devices increases. At the same time the IDDQ current of good devices changes due to process variations and test vector dependencies. Consequently, differentiating good and bad devices by using a simple threshold value for the IDDQ current becomes infeasible.Instead, post-processing techniques are typically applied to handle IDDQ variations. Current signatures [2] are a sorted plot of measured IDDQ values. Discontinuities in this curve typically indicate a fault. Delta-IDDQ [3] is an improvement that compares the differences between measurements and yields more accurate information. These techniques and similar approaches [4] help to remove certain effects coming from process variations and from test vector dependencies.In contrast to these approaches the technique of [5] is applied before the measurement during Automatic Test Pattern Generation (ATPG). By this, leakage variations coming from test vector dependencies are drastically reduced. An IDDQ model predicts the expected leakage current for a given test vector. Then, a small range for IDDQ is defined. Only test vectors within this range are created by the ATPG tool. Figure 1 shows the resulting leakage signatures. No restrictions (α = ∞) yield test vectors across a wide range of leakage values. Tight restrictions (α = 0.5) yield an almost linear curve with a small slope while keeping high fault coverage. Consequently, good and bad devices can be differentiated more easily by IDDQ testing. But no complete ATPG algorithm was given, instead a simple heuristic was applied to generate test vectors. That approach cannot decide whether no test vector within the defined range exists.Algorithms for input vector control [6], [7], [8] search for the input assignment causing the lowest quiescent current for a circuit. Thus, a single optimization problem is solved.

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“…The reason for this choice is that faults with higher detection times tend to be more difficult to detect, and test sequences that detect them tend to be longer, and tend to detect a larger number of additional faults. Procedure 1: The overall sequence selection procedure (1) Simulate T 0 to find the set of detected faults F. For every f ∈ F, store in u det ( f ) the first time unit where f is detected. Set…”

Section: The Basic Proceduresmentioning

confidence: 99%

“…The flip-flops are driven by the combinational logic of the circuit and clocked at-speed in the same way as during the normal operation of the circuit. At-speed testing is important in detecting defects that affect the timing behavior of a circuit [1], [2]. As the accuracy of automatic test equipment (ATE) falls behind clock speeds of VLSI chips, on-chip generation and application of at-speed tests becomes an important alternative to ATE-based test application.…”

Section: Introductionmentioning

confidence: 99%

Built-in test sequence generation for synchronous sequential circuits based on loading and expansion of test subsequences

Pomeranz¹,

Reddy²

Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361)

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We describe an on-chip test generation scheme for synchronous sequential circuits that allows at-speed testing of such circuits. The proposed scheme is based on loading of (short) input sequences into an on-chip memory, and expansion of these sequences on-chip into test sequences. Complete coverage of modeled faults is achieved by basing the selection of the loaded sequences on a deterministic test sequence T 0 , and ensuring that every fault detected by T 0 is detected by the expanded version of at least one loaded sequence. Experimental results presented for benchmark circuits show that the length of the sequence that needs to be stored at any time is on the average 10% of the length of T 0 , and that the total length of all the loaded sequences is on the average 46% of the length of T 0 .

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IDDQ and AC scan: the war against unmodelled defects

Cited by 131 publications

References 18 publications

A Fault Dependent Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint

A Fault Dependent Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint

Deterministic Algorithms for ATPG under Leakage Constraints

Built-in test sequence generation for synchronous sequential circuits based on loading and expansion of test subsequences

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