Abstract:Power devices are operated under harsh conditions, such as high currents and voltages, and so degradation of these devices is an important issue. Our group previously found significant increases in reverse leakage current after applying continuous forward current stress to GaN p–n junctions. In the present study, we identified the type of threading dislocations that provide pathways for this reverse leakage current. GaN p–n diodes were grown by metalorganic vapor phase epitaxy on freestanding GaN(0001) substra… Show more
“…Screw-type dislocations could not be found by STEM and correlated to the cAFM images due to their much lower concentration. However, as described in multiple reports 9 – 11 , 20 these dislocations should be the main cause for the leakage in GaN devices. Figure 6 STEM image of undissociated mixed-type dislocation.…”
Section: Resultsmentioning
confidence: 84%
“…5 b). This sample exhibits a typical step-terrace morphology on which only screw and mixed-type threading dislocations are expected to interact and terminate the terraces 12 , 20 . These dislocations are encircled in black.…”
This work reports the epitaxial growth of 8.5 µm-thick GaN layers on 200 mm engineered substrates with a polycrystalline AlN core (QST by QROMIS) for CMOS compatible processing of vertical GaN power devices. The epitaxial stack contains a 5 $$\upmu$$
μ
m thick drift layers with a Si doping density of 2 × 1016 cm−3 and total threading dislocation density of 4 × 108 cm−2. The thick drift layer requires fine-tuning of the epitaxial growth conditions to keep wafer bow under control and to avoid the formation of surface defects. Diode test structures processed with this epitaxial stack achieved hard breakdown voltages > 750 V, which is shown to be limited by impurity or metal diffusion from the contact metal stack into threading dislocations. Conductive Atomic Force Microscopy (cAFM) reveals some leakage contribution from mixed type dislocations, which have their core structure identified as the double 5/6 atom configuration by scanning transmission electron microscopy images. Modelling of the leakage conduction mechanism with one-dimensional hopping conduction shows good agreement with the experimental data, and the resulting fitting parameters are compared to similar findings on silicon substrates. The outcome of this work is important to understand the possibilities and limitations of vertical GaN devices fabricated on large diameter wafers.
“…Screw-type dislocations could not be found by STEM and correlated to the cAFM images due to their much lower concentration. However, as described in multiple reports 9 – 11 , 20 these dislocations should be the main cause for the leakage in GaN devices. Figure 6 STEM image of undissociated mixed-type dislocation.…”
Section: Resultsmentioning
confidence: 84%
“…5 b). This sample exhibits a typical step-terrace morphology on which only screw and mixed-type threading dislocations are expected to interact and terminate the terraces 12 , 20 . These dislocations are encircled in black.…”
This work reports the epitaxial growth of 8.5 µm-thick GaN layers on 200 mm engineered substrates with a polycrystalline AlN core (QST by QROMIS) for CMOS compatible processing of vertical GaN power devices. The epitaxial stack contains a 5 $$\upmu$$
μ
m thick drift layers with a Si doping density of 2 × 1016 cm−3 and total threading dislocation density of 4 × 108 cm−2. The thick drift layer requires fine-tuning of the epitaxial growth conditions to keep wafer bow under control and to avoid the formation of surface defects. Diode test structures processed with this epitaxial stack achieved hard breakdown voltages > 750 V, which is shown to be limited by impurity or metal diffusion from the contact metal stack into threading dislocations. Conductive Atomic Force Microscopy (cAFM) reveals some leakage contribution from mixed type dislocations, which have their core structure identified as the double 5/6 atom configuration by scanning transmission electron microscopy images. Modelling of the leakage conduction mechanism with one-dimensional hopping conduction shows good agreement with the experimental data, and the resulting fitting parameters are compared to similar findings on silicon substrates. The outcome of this work is important to understand the possibilities and limitations of vertical GaN devices fabricated on large diameter wafers.
“…For the receive side, low-noise amplifiers with high linearity are desired. (Malakoutian et al, 2021;Narita et al, 2022;Tanaka et al, 2017;Tsao et al, 2018;Woo et al, 2022)] Power/High-Frequency Electronics…”
Section: Variability and Error Propagation In Low-energy Processesmentioning
Microelectronics is a complex field with ever-evolving technologies and business needs, fueled by decades of continued fundamental materials science and engineering advancement. Decades of dimensional scaling have led to the point where even the name microelectronics inadequately describes the field, as most modern devices operate on the nanometer scale. As we reach physical limits and seek more efficient ways for computing, research in new materials may offer alternative design approaches that involve much more than electron transport e.g. photonics, spintronics, topological materials, and a variety of exotic quasi-particles. New engineering processes and capabilities offer the means to take advantage of new materials designs e.g. 3D integration, atomic scale fabrication processes and metrologies, digital twins for semiconductor processes and microarchitectures. The wide range of potential technological approaches provides both opportunities and challenges. The Materials, Processes, and R and D Challenges in Microelectronics Future Directions workshop was held June 23-24, 2022, at the Basic Research Innovation Collaboration Center in Arlington, VA, to examine these opportunities and challenges. Sponsored by the Basic Research Directorate of the Office of the Under Secretary of Defense for Research and Engineering, it is intended as a resource for the S and T community including the broader federal funding community, federal laboratories, domestic industrial base, and academia.
“…Elongation of the dislocation cluster generated from a scratch on a (0001) GaN wafer to the surface of the epitaxial layer was reported [11]. The threading screw dislocation (b//[0001]) that is presumed to be the leak path of a GaN pn-diode [12][13][14] is included in the dislocation cluster [11]. Therefore, completely removing the affected layer on 4H-SiC or a GaN wafer is indispensable.…”
With the aim of developing a method of estimating the thickness of an affected layer on a wide-bandgap semiconductor wafer caused by scratching, we investigated the dependence of dislocation pattern size on the width of the imprint (or scratch) induced by the Berkovich indentation (or scratching) using a Berkovich indenter. We found that the penetration depth and width of the dislocation pattern induced on (0001) GaN by indentation are approx. 0.9 times and 30 times that of the imprint width and the imprint depth, respectively. Based on the linearity between the imprint width and the square root of load, the constant hardness is confirmed to be 0.1 mN or more. In comparison to laterally expanding dislocation generation, inclined dislocation generation has a lower threshold load. The cause of this threshold discrepancy is discussed based on the imperfection of the indenter tip. The scratch width linearly increased with the square root of load in the range of 0.5–7 mN. The width and depth of the dislocation pattern induced by the scratch are approx. 11–13 and 0.75–1 times the scratch width, respectively. The width of the dislocation pattern of the [11 ̅00] scratch is larger than that of the [112 ̅0] scratch, however, the penetration depth of the dislocation pattern of [11 ̅00] is smaller than that of [112 ̅0]. These findings indicate that estimating the affected layer thickness induced by mechanical polishing or grinding is possible only by finding the widest scratch on a wafer.
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