Identifying design systematics using learning based diagnostic analysis

Desineni, R.; Pastel, Leah; Kassab, Maroun; Fayaz, Mohammed; Lee, Julie

doi:10.1109/asmc.2010.5551472

Cited by 17 publications

(21 citation statements)

References 6 publications

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“…This is evident in several recently published papers that demonstrate innovative use of volume diagnosis. On-going diagnoses are used as yield learning techniques to identify systematic defects [25,39,49,[73][74][75]82] and derive important information that includes, for example, design-feature failure rates [76,77]. In [24,78], the effectiveness of a given set of DFM rules is evaluated using volume diagnosis results.…”

Section: Chapter 4 Defect Simulationmentioning

confidence: 99%

“…In fact, SLIDER can be used to evaluate any test/yield learning techniques that are based on failure data analysis. For example, consider the evaluation of a systematic defect identification methodology [25,39,49,[73][74][75]82]. Using SLIDER, random and systematic defects can be generated in different proportions to evaluate how much "noise" the methodology can tolerate and still provide the right answer.…”

Section: Framework Usagementioning

confidence: 99%

“…Volume diagnosis refers to the process of performing software-based diagnoses of a large amount of IC test fail data, which is further analyzed for a variety of purposes. For example, on-going diagnoses are used to identify systematic defects [25,49,[73][74][75] and derive design-feature failure rates [76,77]. In [24,78], the effectiveness of DFM is evaluated using volume diagnosis results.…”

Section: Introductionmentioning

confidence: 99%

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Physically-Aware Analysis of Systematic Defects in Integrated Circuits

Tam¹,

Blanton

2012

IEEE Des. Test. Comput.

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In the integrated circuit (IC) industry, all products must go through three phases before they are available in the market, namely design, manufacturing, and testing. Design, obviously, refers to the process of converting the early concepts of the product into a precise description of its implementation. Manufacturing then uses this description to fabricate the product, where the design is physically materialized onto the silicon wafer and later packaged into the product. If design and manufacturing are perfect, then every fabricated IC is completely functional, thereby obliterating the need for testing. Unfortunately, both design and manufacturing are not ideal; therefore every manufactured IC must be subject to stringent testing procedures to ensure that most bad ICs are identified and prevented from shipping to the end-users.ICs are deemed bad when they contain certain defects that cause the ICs to fail the specifications.Defects are unintended structural and/or material changes of the IC due to design/manufacturing imperfections.These physical changes may alter the electrical characteristics of the circuit, which are sometimes severe enough to lead to a failure (i.e., violation of one or more design specifications). Common defects in IC manufacturing can be caused by contaminations in the process, variations of the process conditions, or simply the difficulty to fabricate certain features of the design. The last issue is the focus of this dissertation. Defects that arise due to certain aspects of the design being sensitive to the manufacturing process with an elevated likelihood of failure are known as systematic defects. This dissertation addresses the issues related to the prevention and identification of systematic defects by analyzing a large amount of manufactured ICs that have failed testing.For systematic-defect prevention, one common approach is to use design-for-manufacturability (DFM) rules to communicate hard-to-manufacture features to designers so that these features can be minimized in the iii design. Obviously, different rules describe different features and thus their violation/adherence will have different impact on the manufacturability of the product. It is therefore desirable to measure the relative importance of the rules and how they affect product yield. To address this issue, a method called RADAR (Rule Assessment of Defect-Affected Regions) has been developed for measuring the effectiveness of DFM rules in preventing systematic defects. RADAR analyzes a large amount of test data of failed ICs to draw statistical conclusion.Taking preventive measures, such as enforcing DFM rules, is necessary to ensure sufficient product yield. Unfortunately, the amount of resource (circuit area, designer's time, etc.) dedicated to DFM can be quite limited. It is therefore impractical to anticipate and prevent every possible hard-to-manufacture design features before the product is manufactured. Thus, systematic defects can still exist. Therefore, a mechanism is required to identify systematic ...

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Section: Chapter 4 Defect Simulationmentioning

confidence: 99%

Section: Framework Usagementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Physically-Aware Analysis of Systematic Defects in Integrated Circuits

Tam¹,

Blanton

2012

IEEE Des. Test. Comput.

View full text Add to dashboard Cite

show abstract

“…Volume diagnosis refers to the process of performing software-based diagnoses of a large amount of IC test fail data, which is further analyzed for a variety of purposes. For example, on-going diagnoses are used to identify systematic defects [3][4][5][6][7] and derive design-feature failure rates [8,9]. In [10,11], the effectiveness of DFM is evaluated using volume diagnosis results.…”

Section: Introductionmentioning

confidence: 99%

“…To address these issues, volume diagnosis is increasingly deployed to improve/supplement yield-learning [3][4][5][6][7][8][9][10][11][12][13][14]. Volume diagnosis refers to the process of performing software-based diagnoses of a large amount of IC test fail data, which is further analyzed for a variety of purposes.…”

Section: Introductionmentioning

confidence: 99%