IEEE Std P1838: DfT standard-under-development for 2.5D-, 3D-, and 5.5D-SICs

Marinissen, Erik Jan; McLaurin, Teresa; Jiao, Hailong

doi:10.1109/ets.2016.7519330

Cited by 31 publications

(16 citation statements)

References 13 publications

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“…test features, such as IEEE Std 1149.1 [98], to limit the cost and need for novel tools when testing 3D chips [107], [114]. An interesting consideration is whether these efforts allow to streamline the test of heterogeneous 3D interposer.…”

Section: Discussionmentioning

confidence: 99%

“…7 Test access mechanisms as proposed in IEEE Std P1838 [114] for (a) stacked 3D ICs and (b) interposer-based chips. For both configurations, IEEE Std P1838 utilizes IEEE Std 1149.1 [98] for access control and IEEE Std 1500 [99] for the wrapper.…”

Section: Discussionmentioning

confidence: 99%

“…For both configurations, IEEE Std P1838 utilizes IEEE Std 1149.1 [98] for access control and IEEE Std 1500 [99] for the wrapper. The mechanisms rely on the following signals: TDI/TDO (test data input/output), TMS (test mode select), TCK (test clock), TRSTn (test reset not) [114].…”

Section: Discussionmentioning

confidence: 99%

“…At the same time, 3D integration can help to secure the systemlevel test procedure, thanks to the die wrappers proposed in IEEE Std P1838 [114]. That is because any sensitive information about the die's assets (required for ATPG) can be concealed from an untrusted OSAT party, assuming that the designers provide the test patterns along with the dies.…”

Section: Securing the Test Infrastructure And Test Proceduresmentioning

confidence: 99%

“…Further on-chip structures are needed to isolate and access the interposer and the dies from the external I/Os. This access is defined by IEEE Std P1838 [114], which is reviewed next.…”

Section: Mid-bond Post-bond and Final Testingmentioning

confidence: 99%

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Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Knechtel

Sinanoglu

Elfadel

et al. 2017

IPSJ Transactions on System LSI Design Methodology

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Three-dimensional (3D) integration of electronic chips has been advocated by both industry and academia for many years. It is acknowledged as one of the most promising approaches to meet ever-increasing demands on performance, functionality, and power consumption. Furthermore, 3D integration has been shown to be most effective and efficient once large-scale integration is targeted for. However, a multitude of challenges has thus far obstructed the mainstream transition from "classical 2D chips" to such large-scale 3D chips. In this paper, we survey all popular 3D integration options available and advocate that using an interposer as system-level integration backbone would be the most practical for large-scale industrial applications and design reuse. We review major design (automation) challenges and related promising solutions for interposer-based 3D chips in particular, among the other 3D options. Thereby we outline (i) the need for a unified workflow, especially once full-custom design is considered, (ii) the current design-automation solutions and future prospects for both classical (digital) and advanced (heterogeneous) interposer stacks, (iii) the state-of-art and open challenges for testing of 3D chips, and (iv) the challenges of securing hardware in general and the prospects for large-scale and trustworthy 3D chips in particular.

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Section: Discussionmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%

Section: Securing the Test Infrastructure And Test Proceduresmentioning

confidence: 99%

“…Further on-chip structures are needed to isolate and access the interposer and the dies from the external I/Os. This access is defined by IEEE Std P1838 [114], which is reviewed next.…”

Section: Mid-bond Post-bond and Final Testingmentioning

confidence: 99%

See 3 more Smart Citations

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Knechtel

Sinanoglu

Elfadel

et al. 2017

IPSJ Transactions on System LSI Design Methodology

View full text Add to dashboard Cite

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Test Flow Selection for Stacked Integrated Circuits

et al. 2019

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Integrated circuits (ICs) with a single chip (die) are typically tested with a test flow consisting of two test instances: (1) wafer sort for the bare chip and (2) package test for the packaged IC. For ICs with stacked chips -3D Stacked ICs -there are many possible test instances, even more test flows, and no commonly used test flow. In this paper, we propose a test flow selection algorithm (TFSA) to obtain a test flow for a given 3D Stacked IC. The TFSA results in a test flow for a given 3D Stacked IC, such that the expected total test time to produce each good package is minimized. We implemented the TFSA, three straightforward test flow schemes and an exhaustive search, and experimentally compared the test flow schemes on three different test architecture design approaches. The results demonstrate the importance to have methods both to select the test flow and design the test architecture.Publisher's Note Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. Breeta SenGupta received her M.Sc. degree from Indian Institute of Technology, Kharagpur, India, in 2009. She pursues her Ph.D. at the Department of Electrical and Information Technology, Lund University, Sweden. Her area of research includes 3D integration and testing. Breeta is currently engaged in development and verification of RF ASIC at Ericsson, Sweden.

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