III–V MOSFETs with a new self-aligned contact

Zhang, Xingui; Guo, Huan; Ko, Chih-Hsin; Wann, C.; Cheng, Chao-Ching; Lin, Hsia Yu; Chin, Hock-Chun; Gong, Xiao; Lim, Poon Nian; Luo, Guang-Li; Chang, Chun‐Yen; Chien, Chao–Hsin; Han, Zong-You; Huang, Shih-Chiang; Yeo, Yee-Chia

doi:10.1109/vlsit.2010.5556240

Cited by 6 publications

(4 citation statements)

References 3 publications

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“…[1][2][3][4][5][6][7][8][9][10][11][12] High performance III-V MOSFETs require low source and drain (S/D) series resistance R S/D , which includes metal-semiconductor contact resistance. [13][14][15][16][17][18] To achieve low R S/D in III-V FETs, S/D engineering such as selective growth of in situ doped S/D materials [19][20][21] and self-aligned contacts have been employed. [17][18]21,22 Metallic S/D is another attractive option [23][24][25][26] and should preferably be self-aligned to the gate stack.…”

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“…[13][14][15][16][17][18] To achieve low R S/D in III-V FETs, S/D engineering such as selective growth of in situ doped S/D materials [19][20][21] and self-aligned contacts have been employed. [17][18]21,22 Metallic S/D is another attractive option [23][24][25][26] and should preferably be self-aligned to the gate stack. InGaAs channel n-MOSFETs with self-aligned metallic Ni-InGaAs S/D have been demonstrated recently.…”

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Reduction of Off-State Leakage Current in In0.7Ga0.3As Channel n-MOSFETs with Self-Aligned Ni-InGaAs Contact Metallization

Zhang

Guo

Lin

et al. 2011

Electrochem. Solid-State Lett.

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In 0.7 Ga 0.3 As channel n-MOSFETs (metal-oxide-semiconductor field-effect transistors) with Si-doped S/D and self-aligned NiInGaAs contact were demonstrated for the first time. The salicide-like metallization process employed a direct reaction between Ni and Si-doped InGaAs, followed by the removal of the unreacted Ni. As compared with n-MOSFETs with metallic Ni-InGaAs S/D (i.e. no Si doping in S/D), n-MOSFETs with Ni-InGaAs contact formed on Si-doped S/D show significantly improved OFFstate current I OFF in the linear and saturation regions.III-V materials such as Indium Gallium Arsenide (InGaAs) and Indium Arsenide (InAs) have significantly higher electron mobility than Silicon (Si) and are attractive for future high speed low power logic applications. 1-12 High performance III-V MOSFETs require low source and drain (S/D) series resistance R S/D , which includes metal-semiconductor contact resistance. 13-18 To achieve low R S/D in III-V FETs, S/D engineering such as selective growth of in situ doped S/D materials 19-21 and self-aligned contacts have been employed. [17][18]21,22 Metallic S/D is another attractive option 23-26 and should preferably be self-aligned to the gate stack. InGaAs channel n-MOSFETs with self-aligned metallic Ni-InGaAs S/D have been demonstrated recently. 25,26 However, the n-MOSFETs with metallic S/D suffer from high leakage current at metal/semiconductor junctions in S/D regions, leading to high drain to source and drain to body leakage current. Low drain junction leakage is needed to achieve low standby power consumption.In this work, In 0.7 Ga 0.3 As channel n-MOSFETs with Si-doped S/ D and self-aligned Ni-InGaAs contact were demonstrated for the first time. The spacer-less metallization process is similar to salicidation and drives the diffusion of Ni into InGaAs for reaction to form a conductive material. S/D implant (Si) and dopant activation anneal were performed before the metallization to form n-InGaAs/ p-InGaAs junction. The n-MOSFETs with Si-doped S/D and NiInGaAs contact show significantly suppressed off-state current I OFF as compared with n-MOSFETs with metallic Ni-InGaAs S/D. Device FabricationThe fabrication process flow for In 0.7 Ga 0.3 As channel n-MOSFETs with self-aligned Ni-InGaAs contacts is summarized and illustrated in Fig. 1. 2-in. p-type (N A $1 Â 10 19 cm À3 ) InP wafer was used as starting substrates. A 500 nm thick In 0.53 Ga 0.47 As with p-type (Zn doped) doping concentration N A of 2 Â 10 17 cm À3 and a 20 nm thick In 0.7 Ga 0.3 As with N A of 2 Â 10 16 cm À3 were sequentially grown. After pregate cleaning using HCl and NH 4 OH solution, (NH 4 ) 2 S solution was used to passivate the In 03.7 Ga 0.3 As surface for suppression of surface oxidation. The sample was then quickly loaded into an atomic layer deposition (ALD) tool and $7 nm of Al 2 O 3 was deposited. TaN gate electrode (100 nm thick) was deposited by sputtering, patterned by optical lithography and etched by Cl 2 -based plasma.After gate stack formation, one batch of devices (implanted devices) w...

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Reduction of Off-State Leakage Current in In0.7Ga0.3As Channel n-MOSFETs with Self-Aligned Ni-InGaAs Contact Metallization

Zhang

Guo

Lin

et al. 2011

Electrochem. Solid-State Lett.

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“…Figure c summarizes the ρ c values of the primary Ohmic contact examples in GaAs and our works. − Most contactsboth alloyed and nonalloyed Ohmic contactsexhibit ∼10 –5 Ω cm 2 or ∼10 –6 Ω cm 2 for moderately doped or heavily doped GaAs, respectively. However, the novel CF-MIS contact proposed in this work exhibits one of the lowest ρ c values [(1.5 ± 0.6) × 10 –6 Ω cm 2 ] ever obtained, even though the doping concentration of the GaAs substrate was moderate (1 × 10 18 cm –3 ).…”

Section: Resultsmentioning

confidence: 79%

Novel Conductive Filament Metal–Interlayer–Semiconductor Contact Structure for Ultralow Contact Resistance Achievement

Kim

Park

et al. 2018

ACS Appl. Mater. Interfaces

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In the post-Moore era, it is well-known that contact resistance has been a critical issue in determining the performance of complementary metal-oxide-semiconductor (CMOS) reaching physical limits. Conventional Ohmic contact techniques, however, have hindered rather than helped the development of CMOS technology reaching its limits of scaling. Here, a novel conductive filament metal-interlayer-semiconductor (CF-MIS) contact-which achieves ultralow contact resistance by generating CFs and lowering Schottky barrier height (SBH)-is investigated for potential applications in various nanodevices in lieu of conventional Ohmic contacts. This universal and innovative technique, CF-MIS contact, forming the CFs to provide a quantity of electron paths as well as tuning SBH of semiconductor is first introduced. The proposed CF-MIS contact achieves ultralow specific contact resistivity, exhibiting up to ∼×700 000 reduction compared to that of the conventional metal-semiconductor contact. This study proves the viability of CF-MIS contacts for future Ohmic contact schemes and that they can easily be extended to mainstream electronic nanodevices that suffer from significant contact resistance problems.

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“…For instance, Ni-III-V semiconductor compounds showed low contact resistance but poor thermal stability. Nevertheless, the integration of an interlayer between the metal and the semiconductor resulted in thermal stability improvement while availing the self-aligned advantage of this technology [4][5][6]. In addition, non-alloyed Mo contacts to III-V semiconductors have been also identified as a possible solution [7].…”

Section: Introductionmentioning

confidence: 99%

The Role of III-V Substrate Roughness and Deoxidation Induced by Digital Etch in Achieving Low Resistance Metal Contacts

2017

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To achieve low contact resistance between metal and III-V material, transmission-line-model (TLM) structures of molybdenum (Mo) were fabricated on indium phosphide (InP) substrate on the top of an indium gallium arsenide (InGaAs) layer grown by molecular beam epitaxy. The contact layer was prepared using a digital etch procedure before metal deposition. The contact resistivity was found to decrease significantly with the cleaning process. High Resolution Transmission & Scanning Electron Microscopy (HRTEM & HRSTEM) investigations revealed that the surface roughness of treated samples was increased. Further analysis of the metal-semiconductor interface using Energy Electron Loss Spectroscopy (EELS) showed that the amount of oxides (In x O y , Ga x O y or As x O y ) was significantly decreased for the etched samples. These results suggest that the low contact resistance obtained after digital etching is attributed to the combined effects of the induced surface roughness and oxides removal during the digital etch process.

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III–V MOSFETs with a new self-aligned contact

Cited by 6 publications

References 3 publications

Reduction of Off-State Leakage Current in In0.7Ga0.3As Channel n-MOSFETs with Self-Aligned Ni-InGaAs Contact Metallization

Reduction of Off-State Leakage Current in In0.7Ga0.3As Channel n-MOSFETs with Self-Aligned Ni-InGaAs Contact Metallization

Novel Conductive Filament Metal–Interlayer–Semiconductor Contact Structure for Ultralow Contact Resistance Achievement

The Role of III-V Substrate Roughness and Deoxidation Induced by Digital Etch in Achieving Low Resistance Metal Contacts

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