Illegal state extraction from Register Transfer Level

Hobeika, Christelle; Thibeault, Claude; Boland, Jean François

doi:10.1109/newcas.2010.5603786

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2015

2024

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Cited by 3 publications

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“…They then present a method of effectively using this statistical information to guide the ATPG efforts. [70,71] an RTL illegal state extraction methodology based on code parsing and parsing expression grammar (PEG). The extracted values help building functional constraints that are forced during ATPG process in order to generate pseudo-functional test patterns.…”

Section: Thaker Et Al Use Inmentioning

confidence: 99%

A Novel RTL ATPG Model Based on Gate Inherent Faults (GIF-PO) of Complex Gates

Strauch¹

2016

Preprint

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This paper starts with a comprehensive survey on RTL ATPG. It then proposes a novel RTL ATPG model based on "Gate Inherent Faults" (GIF). These GIF are extracted from each complex gate (adder, case-statement, etc.) of the RTL source code individually. They are related to the internal logic paths of a complex gate. They are not related to any net/signal in the RTL design. It is observed, that when all GIF on RTL are covered (100%) and the same stimulus is applied, then all gate level stuck-at faults of the netlist are covered (100%) as well. The proposed RTL ATPG model is therefore synthesis independent. This is shown on ITC'99 testcases. The applied semi-automatic test pattern generation process is based on functional simulation.

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Section: Thaker Et Al Use Inmentioning

confidence: 99%