Image tiling for embedded applications with non-linear constraints

Abstract

Tiling is a key aspect of the design of embedded image processing applications, due to local memory constraints.To maximize system performance, the designer must select a suitable tile size that balances data transfers and computation. In this work, we present a method for optimal 2D image tile sizing using constraint programming. Unlike previous methods, ours accurately models DMA data transfer times and parallel scheduling overheads with non-linear constraints. Our experiments with a binomial filter demonstrate that we can compute the optimal tiling dimensions that minimize the execution time for different image sizes and internal memory constraints. This technique provides invaluable information for both application developers and system architects that can quickly explore design trade-offs.

Virtual Address Remapping with Configurable Tiles in Image Processing Applications

“…(3) Address tiling: A number of tiled address maps for efficient memory accesses are reported. In [8], the tile sizing algorithm using the constraint programming is presented. In [9], an MMU performance for various tile sizes is analyzed.…”

Adaptive Linear Address Map for Bank Interleaving in DRAMs

“…In the master side, a number of address maps for efficient memory accesses are reported. In [15]- [17], a tiled address layout is presented. In [15], the image tile sizing algorithm using the constraint programming is presented.…”

“…In [15]- [17], a tiled address layout is presented. In [15], the image tile sizing algorithm using the constraint programming is presented. In [16], the 4D tile format is presented.…”

“…Metric i,j is calculated by summing up Metric adj in the northern (N), the southern (S), the eastern (E), and the western (W) directions. As an example, for the transaction 15 in Fig. 6(a), Metric 1,3 is 5 (= 1+1+1+2).…”