Imaging X-ray detector front-end with high dynamic range: IDeF-X HD

Gevin, O.; Lemaire, Olivier O.; Lugiez, F.; Michalowska, Alicja; Baron, P.; Limousin, O.; Delagnes, É.

doi:10.1016/j.nima.2011.11.020

Cited by 39 publications

(18 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It was built based on the AMS CMOS 0.35 µm technology using the full custom Rad-Hard libraries, and combine the most recent developments for space applications, including fully space-qualified devices [64,90]. In particular, IDeF-X HD was extensively studied with respect to radiation tolerance (Single Event Latchup (SEL) -free; Single Event Effect (SEE) > 9 MeV cm 2 mg −1 ; Total Ionizing Dose (TID) > 300 krad w/o effect on noise response), as it was selected for the FEE of the STIX instrument of the Solar Orbiter mission.…”

Section: Silicon Trackermentioning

confidence: 99%

The e-ASTROGAM mission

et al. 2017

Self Cite

View full text Add to dashboard Cite

e-ASTROGAM ('enhanced ASTROGAM') is a breakthrough Observatory space mission, with a detector composed by a Silicon tracker, a calorimeter, and an anticoincidence system, dedicated to the study of the non-thermal Universe in the photon energy range from 0.3 MeV to 3 GeV -the lower energy limit can be pushed to energies as low as 150 keV, albeit with rapidly degrading angular resolution, for the tracker, and to 30 keV for calorimetric detection. The mission is based on an advanced space-proven detector technology, with unprecedented sensitivity, angular and energy resolution, combined with polarimetric capability. Thanks to its performance in the MeV-GeV domain, substantially improving its predecessors, e-ASTROGAM will open a new window on the non-thermal Universe, making pioneering observations of the most powerful Galactic and extragalactic sources, elucidating the nature of their relativistic outflows and their effects on the surroundings. With a line sensitivity in the MeV energy range one to two orders of magnitude better than previous generation instruments, e-ASTROGAM will determine the origin of key isotopes fundamental for the understanding of supernova explosion and the chemical evolution of our Galaxy. The mission will provide unique data of significant interest to a broad astronomical community, complementary to powerful observatories such as LIGO-Virgo-GEO600-KAGRA, SKA, ALMA, E-ELT, TMT, LSST, JWST, Athena, CTA, IceCube, KM3NeT, and the promise of eLISA.

show abstract

Section: Silicon Trackermentioning

confidence: 99%

The e-ASTROGAM mission

et al. 2017

Self Cite

View full text Add to dashboard Cite

show abstract

“…In case of, for example ultra-wideband data transmission and radio technology [5,6], microwave communications, ultrasound imaging [7], oscilloscope probe amplifiers or radiation detectors [8,9], the parasitic capacitance at the input pin can dramatically degrade performance [10]. These applications involve signal sensing and processing, therefore low noise is a key parameter in the above examples.…”

Section: Fig 1 Ic Io Pin Protected By On-chip Esd Devicementioning

confidence: 99%

Design and theoretical comparison of input ESD devices in 180 nm CMOS with focus on low capacitance

Michalowska-Forsyth

Schrey

Deutschmann

2018

Elektrotech. Inftech.

View full text Add to dashboard Cite

With the last decade's advances in sensor technologies and packaging techniques, there are several applications where the input capacitance and the leakage current of the integrated circuit (IC) front-end limit the readout accuracy of sensor systems. In particular, optimization of the electrostatic discharge (ESD) protection devices at the IC input could improve performance. Specifically, such optimization should involve reduction of parasitic capacitance and leakage current while maintaining the ESD robustness. Several ESD devices have been analyzed against input capacitance, leakage current and robust ESD performance. The first device of interest is a diode, as the simplest solution and then there are three MOS transistor based devices, gate-grounded NMOS (GGNMOS), gatecoupled NMOS (GCNMOS), and substrate pump NMOS (SPNMOS). The target fabrication process is 180 nm CMOS. Theoretical analysis of capacitance simulated with Cadence ® in 180 nm CMOS design kit including layout extracted parasitics in combination with TCAD Sentaurus ® simulations of current density and temperature is presented for selected ESD devices.Keywords: electrostatic discharge; integrated circuit; robust; ESD diode; GGNMOS Design und theoretischer Vergleich von ESD-Schutzstrukturen in 180 nm CMOS mit Schwerpunkt auf geringen Eingangskapazitäten. Mit den Fortschritten des letzten Jahrzehnts in Sensor-und IC-Package-Technologien gibt es vermehrt Anwendungen, bei denen die Eingangskapazität und der Leckstrom des integrierten Schaltkreises (ICs) die Auslesegenauigkeit von Sensorsystemen begrenzen. Eine entsprechende Optimierung der Schutzstrukturen gegen elektrostatische Entladungen (ESD) an den Eingängen der ICs könnte die Performance verbessern. Eine solche Optimierung sollte insbesondere eine Verringerung der parasitären Kapazität und des Leckstroms beinhalten, während die ESD-Robustheit beibehalten wird. Mehrere ESD-Schutzstrukturen wurden auf ihre Eingangskapazität, ihren Motivation and methodsESD protection devices shield integrated circuit from damage during an ESD event. Although the most powerful events should be typically handled by the system-level off-chip protection device, but ESD protection concept is obligatory already at the component-level (Fig. 1). ESD robustness is characterized by applying standardized tests [1]. These tests differ for components and systems. On the one hand, component-level ESD tests evaluate if a single component, e.g. an IC, is able to withstand fabrication, package, handling, and assembly. The device under test (DUT) in a component-level test is not powered. Hence, malfunctions cannot be detected and component-level tests cover physical damage, so called hard failures only. On the other hand, system-level ESD tests aim to detect any malfunction of an electronic system, e.g. mobile phone. These are not restricted to hard failures and include any disturbance of operation like an unintentional reset or display black-out. These failures are known as soft failures. System-level ESD tests usually feature mor...

show abstract

“…For the high-density read-out of the detector dedicated ASICs with very good performance and low power (17 e -rms noise with 650 µW/channel) are needed. For the M4 configuration, the read-out is performed by 8x 32-channel IDeF-X HD ASICs [25], with A/D conversion carried out by 1x 16-channel OWB-1 ASIC for every detector. The dynamic range of the read-out electronics is required to record events with energy up to 80 keV.…”

Section: Large Area Detector (Lad)mentioning

confidence: 99%