Impact of a Spacer–Drain Overlap on the Characteristics of a Silicon Tunnel Field-Effect Transistor Based on Vertical Tunneling

Mallik, Abhijit; Chattopadhyay, Avik; Guin, Shilpi; Karmakar, Anupam

doi:10.1109/ted.2013.2237776

Cited by 55 publications

(22 citation statements)

References 20 publications

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“…The dual-source regions are located on two sides of the gate (sapphire regions). Two n+ pockets (yellow regions) are inserted to increase the channel tunneling rate [20][21][22]. The n+ drain is placed in the bottom of the channel.…”

Section: Methodsmentioning

confidence: 99%

“…However, due to the small effective tunneling area, the limited tunneling current becomes an inherent disadvantage in conventional P-I-N TFET, which leads to a low on-state operating current (I ON ). In order to improve the TFET performance, many new structures have been proposed in recent years [20][21][22][23][24][25]. Benefiting from the recessed gate, L-shape tunnel field-effect transistor (LTFET) [23,24] and U-shape tunnel field-effect transistor (UTFET) [25] have been proposed to obtain high I ON with a compact device structure.…”

Section: Introductionmentioning

confidence: 99%

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Analog/RF Performance of T-Shape Gate Dual-Source Tunnel Field-Effect Transistor

et al. 2018

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In this paper, a silicon-based T-shape gate dual-source tunnel field-effect transistor (TGTFET) is proposed and investigated by TCAD simulation. As a contrastive study, the structure, characteristic, and analog/RF performance of TGTFET, LTFET, and UTFET are discussed. The gate overlap introduced by T-shape gate can enhance the efficiency of tunneling junction. The dual-source regions in TGTFET can increase the on-state current (ION) by offering a doubled tunneling junction area. In order to further improve the device performance, the n+ pocket is introduced in TGTFET to further increase the band-to-band tunneling rate. Simulation results reveal that the TGTFET’s ION and switching ratio (ION/IOFF) reach 81 μA/μm and 6.7 × 1010 at 1 V gate to source voltage (Vg). The average subthreshold swing of TGTFET (SSavg, from 0 to 0.5 V Vg) reaches 51.5 mV/dec, and the minimum subthreshold swing of TGTFET (SSmin, at 0.1 V Vg) reaches 24.4 mV/dec. Moreover, it is found that TGTFET have strong robustness on drain-induced barrier lowering (DIBL) effect. The effects of doping concentration, geometric dimension, and applied voltage on device performance are investigated in order to create the TGTFET design guideline. Furthermore, the transconductance (gm), output conductance (gds), gate to source capacitance (Cgs), gate to drain capacitance (Cgd), cut-off frequency (fT), and gain bandwidth (GBW) of TGTFET reach 232 μS/μm, 214 μS/μm, 0.7 fF/μm, 3.7 fF/μm, 11.9 GHz, and 2.3 GHz at 0.5 V drain to source voltage (Vd), respectively. Benefiting from the structural advantage, TGTFET obtains better DC/AC characteristics compared to UTFET and LTFET. In conclusion, the considerable good performance makes TGTFET turn into a very attractive choice for the next generation of low-power and analog/RF applications.

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Section: Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Analog/RF Performance of T-Shape Gate Dual-Source Tunnel Field-Effect Transistor

et al. 2018

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“…However, there are also inherent disadvantages in TFETs, such as the small on-state current and large miller capacitance [13]. To improve the on-state current of TFET, new device structures are proposed, such as the L-channel tunneling field effect transistor (LTFET) [14,15], U-channel tunneling field effect transistor (UTFET) [16], heterojunction tunneling field effect transistor (HTFET) [17], and T-shaped gate tunneling field effect transistor (HTG-TFET) [18,19]. To achieve the tunneling effectively, it is necessary to form the highly doped abrupt junction in these novel device structures.…”

Section: Introductionmentioning

confidence: 99%

Design and Investigation of the Junction-Less TFET with Ge/Si0.3Ge0.7/Si Heterojunction and Heterogeneous Gate Dielectric

et al. 2019

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To improve the on-state current and reduce the miller capacitance of the conventional junction-less tunneling field effect transistor (JLTFET), the junction-less TFET with Ge/Si0.3Ge0.7/Si heterojunction and heterogeneous gate dielectric (H-JLTFET) is investigated by the Technology Computer Aided Design (TCAD) simulation in this paper. The source region uses the narrow bandgap semiconductor material germanium to obtain the higher on-state current; the gate dielectric adjacent to the drain region adopts the low-k dielectric material SiO2, which is considered to reduce the gate-to-drain capacitance effectively. Moreover, the gap region uses the Si0.3Ge0.7 material to decrease the tunneling distance. In addition, the effects of the device sizes, doping concentration and work function on the performance of the H-JLTFET are analyzed systematically. The optimal on-state current and switching ratio of the H-JLTFET can reach 6 µA/µm and 2.6 × 1012, which are one order of magnitude and four orders of magnitude larger than the conventional JLTFET, respectively. Meanwhile, the gate-to-drain capacitance, off-state current and power consumption of the H-JLTFET can be effectively suppressed, so it will have a great potential in future ultra-low power integrated circuit applications.

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“…In this paper, the spacer engineering of DGTFET is optimized to make DGTFET obtain the optimum performance. In TFETs, the spacer dielectrics have the strong influences on BTBT [ 22 , 23 ]. In DGTFET, the spacers at the source and drain sides are closed to tunneling junctions, so they greatly affect the performance of DGTFET DRAM.…”

Section: Introductionmentioning

confidence: 99%

The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor

Liu

Wang

et al. 2018

Nanoscale Res Lett

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The DRAM based on the dual-gate tunneling FET (DGTFET) has the advantages of capacitor-less structure and high retention time. In this paper, the optimization of spacer engineering for DGTFET DRAM is systematically investigated by Silvaco-Atlas tool to further improve its performance, including the reduction of reading “0” current and extension of retention time. The simulation results show that spacers at the source and drain sides should apply the low-k and high-k dielectrics, respectively, which can enhance the reading “1” current and reduce reading “0” current. Applying this optimized spacer engineering, the DGTFET DRAM obtains the optimum performance-extremely low reading “0” current (10−14A/μm) and large retention time (10s), which decreases its static power consumption and dynamic refresh rate. And the low reading “0” current also enhances its current ratio (107) of reading “1” to reading “0”. Furthermore, the analysis about scalability reveals its inherent shortcoming, which offers the further investigation direction for DGTFET DRAM.

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Impact of a Spacer–Drain Overlap on the Characteristics of a Silicon Tunnel Field-Effect Transistor Based on Vertical Tunneling

Cited by 55 publications

References 20 publications

Analog/RF Performance of T-Shape Gate Dual-Source Tunnel Field-Effect Transistor

Analog/RF Performance of T-Shape Gate Dual-Source Tunnel Field-Effect Transistor

Design and Investigation of the Junction-Less TFET with Ge/Si0.3Ge0.7/Si Heterojunction and Heterogeneous Gate Dielectric

The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor

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