Impact of Channel, Stress-Relaxed Buffer, and S/D Si1−xGe x Stressor on the Performance of 7-nm FinFET CMOS Design with the Implementation of Stress Engineering

Othman, N. A. F.; Hatta, Sharifah Fatmadiana Wan Muhamad; Soin, Norhayati

doi:10.1007/s11664-017-6058-8

Cited by 6 publications

(3 citation statements)

References 48 publications

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“…During the downscaling of MOSFET, the thickness of gate oxide has steadily decreased to increase the gate capacitance and drive current, thus raising the device performance. However, leakage current due to tunnelling increase drastically when the thickness of gate oxide falls below 2nm, thus leading to high power consumption and low device reliability [5]. To overcome various limitations on physical downscaling, leading industries plan to migrate from FinFET architecture in 5nm process node to GAA NWFET architecture in 3nm process node [6][7] since GAA NWFET architecture allows up to 35% decrease in area, 50% decrease in power consumption and 30% improve in performance as compared to the FinFET architecture.…”

Section: Introductionmentioning

confidence: 99%

Process variations and short channel effects analysis in gate-all-around nanowire field-effect transistor using a statistical Taguchi-Pareto ANOVA framework

Yau

Hatta

Wahab

et al. 2022

Preprint

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Gate-all-around nanowire field-effect transistor (GAA NWFET) is a viable alternative to reduce short channel effects. A 3D model of the GAA NWFET was explored by studying the effect of process parameters such as nanowire materials, gate oxide materials and high-κ coverage angles on vital transistor performance metrices specifically threshold voltage, leakage current, current ratio, subthreshold swing (SS) and drain induce barrier lowering (DIBL). It has been observed that the nanowire material of InP provides the lowest threshold voltage and highest drive current. Gate oxide material of HfO2 showed improved leakage current by 88.39%, current ratio by 1439.63%, SS by 24.16% and DIBL by 13.11% relative to the conventional NWFET with SiO2 gate oxide. Moreover, as the high-κ dielectric (HfO2) covers the gate oxide over the channel region, the gate electrostatic control over the channel region increases, thus reducing SS to an ideal value. An exhaustive Taguchi Method with Conceptual Signal-To-Noise Ratio Approach and Pareto Analysis of Variance optimization was conducted to determine the optimal design for high current ratio and low threshold voltage. This work inherently provides a framework in designing an optimized GAA NWFET by considering the device’s highest to lowest domineering design factors in affecting its performance matrices.

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Section: Introductionmentioning

confidence: 99%

Process variations and short channel effects analysis in gate-all-around nanowire field-effect transistor using a statistical Taguchi-Pareto ANOVA framework

Yau

Hatta

Wahab

et al. 2022

Preprint

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“…Strained Ge films are now expected as future channel materials for pMOS due to their high hole mobility [5][6][7]. In this case, high-Ge-content constant-composition SiGe (CC-SG)/compositionally graded SiGe strain-relaxed buffer (graded SRB) stacked structures on Si(001) wafers play the role of feasible stressors [8][9][10]. Here, the graded SRBs having continuously increased Ge content in step with the growth result in a reduction of the dislocation density of the CC-SG layers grown on them.…”

Section: Introductionmentioning

confidence: 99%

Depth-resolved analysis of lattice distortions in high-Ge-content SiGe/compositionally graded SiGe films using nanobeam x-ray diffraction

Shida

Takeuchi

Tohei

et al. 2018

Semicond. Sci. Technol.

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We have investigated the three-dimensional configuration of lattice distortions, including lattice plane tilt and twist, in a high-Ge-content constant-composition Si 0.3 Ge 0.7 (CC-SG)/ compositionally graded SiGe strain-relaxed buffer (graded SRB)/Si(001) stacked structure. Position-dependent ω-2θ-j mapping (or three-dimensional reciprocal space mapping) by synchrotron-based nanobeam x-ray diffraction revealed the in-plane distributions of both local tilt and twist within an area of 10×10 μm on the sample surface. Depth-resolved crystal information was extracted analytically on the basis of structural features in the graded SRB layer. As a result, a series of tomographic maps that show the three-dimensional distributions of tilt and twist around the CC-SG/graded SRB interface were obtained. Tomographic analysis indicates that the orientation of lattice planes in the graded SRB abruptly changes at a specific depth and at a specific interval. The misfit dislocation distribution observed using transmission electron microscopy is not homogeneous but concentrated at a specific depth, which accounts for the abrupt changes of lattice plane tilt and twist. Our tomographic results clearly verify the dislocation morphology in the SiGe stacked structure, which demonstrates that this analysis method can be a powerful tool for quantitative and non-destructive elucidation of a three-dimensional lattice structure with high spatial resolution.

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“…Previous studies contributed considerable efforts in the verification of lattice-strain mechanism and stressed coatings. [13][14][15][16][17][18][19] However, investigations regarding the resultant variation of device performance composed of strainedinduced SHE and local lattice mismatch stressors behind 10 nm nodal technology were never seen. Therefore, this work presents a process-oriented finite element simulation to reflect more actual stress distribution within the testing vehicle of 7 nm Ge p-FinFET accurately.…”

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confidence: 99%

Performance characteristics of strained Ge p-FinFETs under the integration of lattice and self-heating stress enabled by process-oriented finite element simulation

Lee

Hsieh

Huang

et al. 2021

Appl. Phys. Express

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Stress-induced mechanism and related manifold characteristics from lattice mismatch and harsh self-heating effect (SHE) substantially interact are major concerns of advanced strained Ge p-FinFETs with inherent poor thermal conductivity. This study presents a process-oriented simulation methodology to investigate the comprehensive influences composed of the stress amplitude and performance variations induced by SHE and lattice stresses. Device performance can be separately improving by 15.98% and 31.20% when lattice strain and subsequent SHE are introduced. In conclusion, the effect of SHE on the performance of advanced p-FinFET is explored and found tantamount to the stress contribution of the lattice mismatch.

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Impact of Channel, Stress-Relaxed Buffer, and S/D Si1−xGe x Stressor on the Performance of 7-nm FinFET CMOS Design with the Implementation of Stress Engineering

Cited by 6 publications

References 48 publications

Process variations and short channel effects analysis in gate-all-around nanowire field-effect transistor using a statistical Taguchi-Pareto ANOVA framework

Process variations and short channel effects analysis in gate-all-around nanowire field-effect transistor using a statistical Taguchi-Pareto ANOVA framework

Depth-resolved analysis of lattice distortions in high-Ge-content SiGe/compositionally graded SiGe films using nanobeam x-ray diffraction

Performance characteristics of strained Ge p-FinFETs under the integration of lattice and self-heating stress enabled by process-oriented finite element simulation

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