Impact of Cu TSVs on BEOL metal and dielectric reliability

Li, Yunlong; Croes, Kristof; Nabiollahi, Nabi; Huylenbroeck, Stefaan Van; González, Mario; Velenis, Dimitrios; Bender, Hugo; Jourdain, Anne; Pantouvaki, Marianna; Stucchi, M.; Vanstreels, Kris; Peer, Myriam Van De; Messemaeker, Joke De; Wu, Chen; Beyer, Gerald; Wolf, Ingrid De; Beyne, Eric

doi:10.1109/irps.2014.6860630

Cited by 10 publications

(4 citation statements)

References 12 publications

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“…The TSV liner is a 200nm thick O3 TEOS dielectric. Stress-induced-voiding failure rates under vias placed at different locations above a TSV for the case where the TSV is integrated before the BEOL and thus appears directly below the first metal layer (M1) [22].…”

Section: Discussionmentioning

confidence: 99%

“…Alternatively, the use of more vias connected in parallel is recommended as an effective mitigation strategy against SIV. In general, the impact of the TSV presence on BEOL TDDB is low, as shown in [22] at least for BEOL layers processed in the 65nm technology node. As for FEOL, it can be concluded that BEOL reliability is not impacted by the TSV presence if the TSV integration processes and the interconnect layout are optimized.…”

mentioning

confidence: 96%

“…Stress-induced-voiding failure rates under vias placed at different locations above a TSV for the case where the TSV is integrated before the BEOL and thus appears directly below the first metal layer (M1)[22]. FIB cross-section of exposed Cu nail after thermo-cycling for the case where the TSV is integrated before the BEOL (via-middle scheme).…”

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confidence: 99%

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Reliability Challenges Related to TSV Integration and 3-D Stacking

Croes

Messemaeker

et al. 2016

IEEE Des. Test

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Imec's view on the key reliability issues related to 3D integration is discussed. First, throughsilicon via (TSV) reliability concerns linked to thermo-mechanical stresses induced in copper and silicon and to TSV barrier/liner integrity are considered. Then, the possible impact of the TSV on the performance and reliability of nearby devices and interconnects is addressed. After that, reliability concerns related to wafer thinning and backside processing are covered by discussing the effect of stress release in exposed copper nails and the impact of backside passivation and copper contamination on devices. Finally, reliability issues caused by 3D stacking are discussed. KeywordsThrough Silicon Via; Wafer Thinning; 3D-Stacking; Reliability; IntroductionWhile IC dimension scaling leads to faster transistors, the performance of the whole integrated circuit is becoming more and more affected by the increasing signal delay associated with the cross-section scaling of on-chip and off-chip interconnects. 3D integration is one of the most promising technology candidates to mitigate the so-called interconnect bottleneck. With 3D integration, chips are stacked on top of each other, leading to a significant sleek form factor reductions [1][2]. Electrical connections between different stacked chips are made by vertical conductors, the so-called TSVs [3][4], with typical diameters and depths in the range between 2-20m and 10-100m, respectively, in leading-edge processes. TSVs can be processed at different phases of the chip fabrication. With via-first integration, the TSV is fabricated before

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Section: Discussionmentioning

confidence: 99%

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confidence: 96%

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Reliability Challenges Related to TSV Integration and 3-D Stacking

Croes

Messemaeker

et al. 2016

IEEE Des. Test

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“…The literatures investigated the effects of annealing temperature, Cu electroplating parameter, and other factors on pop‐out phenomenon of TSV‐Cu. Moreover, the effects of Cu pop‐out on the dielectric layers directly above the TSV structure and the effects of TSV proximity on devices have been investigated. However, no literature was found to study the impact of TSV structure on BEOL layers around the TSV during the annealing process according to the authors' knowledge.…”

Section: Introductionmentioning

confidence: 99%

Optimization of TSV interconnects and BEOL layers under annealing process through fracture evaluation

Qin

Zhang

Dai

et al. 2020

Fatigue Fract Eng Mat Struct

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Through silicon via (TSV) is a crucial interconnection structure in 3-D integrated circuits. However, protrusion and intrusion of TSV-Cu caused by annealing could lead to cracking and failure of back-end-of-line (BEOL) layers and TSV interconnects due to mismatch of coefficient of thermal expansion. In this paper, optimizations of TSV interconnects and BEOL layers under annealing process are investigated based on fracture evaluation. Influences of geometrical factors including the TSV geometry dimension, the distance between TSV and BEOL layers, and pitch size of Cu via on energy release rate and J-integral are studied for TSV interconnects and BEOL layers with cracks.Effect of material properties for low k dielectrics on interfacial fracture of BEOL layers and TSV interconnects is also given. Optimized geometrical factors and optimized material properties of low k dielectrics are presented in this paper. Fracture-based method sheds a light on emerging electronic packaging optimization. K E Y W O R D Sannealing process, BEOL layer, energy release rate, J-integral, TSV interconnect

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