Reliability Challenges Related to TSV Integration and 3-D Stacking

Abstract

Imec's view on the key reliability issues related to 3D integration is discussed. First, throughsilicon via (TSV) reliability concerns linked to thermo-mechanical stresses induced in copper and silicon and to TSV barrier/liner integrity are considered. Then, the possible impact of the TSV on the performance and reliability of nearby devices and interconnects is addressed. After that, reliability concerns related to wafer thinning and backside processing are covered by discussing the effect of stress release in exposed copper nails and the impact of backside passivation and copper contamination on devices. Finally, reliability issues caused by 3D stacking are discussed. KeywordsThrough Silicon Via; Wafer Thinning; 3D-Stacking; Reliability; IntroductionWhile IC dimension scaling leads to faster transistors, the performance of the whole integrated circuit is becoming more and more affected by the increasing signal delay associated with the cross-section scaling of on-chip and off-chip interconnects. 3D integration is one of the most promising technology candidates to mitigate the so-called interconnect bottleneck. With 3D integration, chips are stacked on top of each other, leading to a significant sleek form factor reductions [1][2]. Electrical connections between different stacked chips are made by vertical conductors, the so-called TSVs [3][4], with typical diameters and depths in the range between 2-20m and 10-100m, respectively, in leading-edge processes. TSVs can be processed at different phases of the chip fabrication. With via-first integration, the TSV is fabricated before

Contactless Heterogeneous 3-D ICs for Smart Sensing Systems

“…Considering these important issues, heterogeneous 3-D integration provides a promising platform for edge devices of the Internet-of-Things comprising multi-functional, small form factor, and low power systems [6]. A heterogeneous 3-D system is composed of stacked integrated circuits, manufactured in disparate technologies.…”

“…Considering inter-tier interconnects, through silicon vias (TSVs) provide high density signalling with low latency and power [8]. However, TSVs entail an overhead in cost due to the related manufacturing complexity and possibly low yield [9,6,10]. For example, to alleviate the impact of copper pumping due to the TSVs, an additional high thermal annealing process is required, increasing the manufacturing cost [6].…”

“…However, TSVs entail an overhead in cost due to the related manufacturing complexity and possibly low yield [9,6,10]. For example, to alleviate the impact of copper pumping due to the TSVs, an additional high thermal annealing process is required, increasing the manufacturing cost [6]. Several other reliability issues need to be considered, such as copper diffusion from the TSV to the substrate, mechanical stresses, and electromigration, each requiring additional processing steps.…”

Efficient Thermal-Stress Coupling Design of Chiplet-Based System with Coaxial TSV Array

“…With the development of semiconductor manufacturing processes, Chiplet-based systems have been widely investigated to achieve the continuation of Moore’s law [ 1 , 2 , 3 ]. Due to the advantages of miniaturization, high performance, and low cost, Chiplet-based systems have been applied in computing systems and processing-in-memory systems [ 4 , 5 , 6 ].…”

Boundary Layers Defect Diagnosis and Analysis of Through Silicon Via (TSV)

“…As a new interconnect technology, TSV technology faces many process difficulties and challenges [10][11]. The reliability has not been fully studied and guaranteed [12]. Identifying defects and analyzing the failure mechanism play important roles in the optimization and improvement of the design, production, and use of TSV 3D integrated devices [13][14][15][16][17][18][19].…”