Impact of Cycling on Random Telegraph Noise in 3-D NAND Flash Arrays

Nicosia, Gianluca; Goda, Akira; Spinelli, A.S.; Compagnoni, Christian Monzio

doi:10.1109/led.2018.2847341

Cited by 20 publications

(15 citation statements)

References 26 publications

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“…The characterization results evidenced that the phenomenon is unlikely ascribed only to a general V T instability that occurs in presence of stochastic charge trapping/de-trapping events in the tunnel-oxide/interface like for RTN [7], [18], [19] since the fail bits increase is localized in the first group of cells read (see Fig. 5).…”

Section: Discussion On the Tre Naturementioning

confidence: 95%

“…So far, several integration options for 3D-NAND reached a fabrication yield and a maturity level good enough for mass production, outmatching at the same time planar technologies in terms of bit density and performance [1], [2], [3]. Concerning reliability, several benchmarks showed that 3D-NAND Flash are better than state-of-the-art 2D NAND Flash [4], [5], [6], although all the issues concerning the cells threshold voltage (V T ) instabilities like Random Telegraph Noise (RTN), cycling and retention failures are inherited to a large extent [7].…”

Section: Introductionmentioning

confidence: 99%

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First Evidence of Temporary Read Errors in TLC 3D-NAND Flash Memories Exiting From an Idle State

Zambelli

Micheloni²,

Scommegna³

et al. 2020

IEEE J. Electron Devices Soc.

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This paper presents a new reliability threat that affects 3D-NAND Flash memories when a read operation is performed exiting from an idle state. In particular, a temporary large increase of the fail bits count is reported for the layers read as first after a sequence of program/verify and a idle retention phase. The phenomenon, hereafter called Temporary Read Errors (TRE), is not due to a permanent change of cell threshold voltage between the program verify and the following read operations, but to its transient instability occurring during the idle phase and the first read operations performed on a block. The experimental analysis has been performed on off-the-shelf gigabit-array products to characterize the dependence on the memory operating conditions. The TRE is found to be strongly dependent on the page read, on the read temperature and on the time delay between the first and the second read after the idle state. To emphasize its negative impact at system-level, we have evaluated the induced performance drop on Solid State Drives architectures. INDEX TERMS 3D-NAND flash, characterization, fail bits, read errors, reliability, solid-state drives (SSD).

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Section: Discussion On the Tre Naturementioning

confidence: 95%

Section: Introductionmentioning

confidence: 99%

First Evidence of Temporary Read Errors in TLC 3D-NAND Flash Memories Exiting From an Idle State

Zambelli

Micheloni²,

Scommegna³

et al. 2020

IEEE J. Electron Devices Soc.

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“…The reduction in the nonuniformities in channel electrostatics with temperature arises both from the reduction in trap occupancy at the grain boundaries [12] and to a less severe constraint of thermionic emission. All of these points must be carefully considered when addressing the variety of phenomena affected by percolative channel conduction, such as RTN [7,13,19,[34][35][36] and charge detrapping [37][38][39][40], when performing spectroscopic analyses of oxide traps based on local tunneling currents [41][42][43][44] and when addressing the impact of localized electron storage in charge trap layers on nonuniform channel inversion [45].…”

Section: Current Variabilitymentioning

confidence: 99%

“…The presence of grains separated by highly defective grain boundaries in the polysilicon channel of the strings introduces some relevant issues in the operation and in the reliability of the array. Among them, it is worth mentioning (i) a severe limitation to the string current, especially at low temperature [7]; (ii) transient instabilities in the string current, due to the dependence of the average occupancy of the traps at the grain boundaries on the bias history of the string [8][9][10]; (iii) variability in the cell threshold voltage ( V T ) and in its temperature dependence, due to the haphazardness in the configuration of the polysilicon grains [11,12]; (iv) the worsening of the amplitude statistics of random telegraph noise (RTN) affecting cell V T , due to the contribution to percolative channel conduction of the nonuniform inversion of the intra-grain and inter-grain regions [13][14][15][16][17][18][19]. The adoption of a thin annular channel instead of a full nanowire was demonstrated to be a successful solution to mitigate some of these issues [20,21].…”

Section: Introductionmentioning

confidence: 99%

A comparison of modeling approaches for current transport in polysilicon-channel nanowire and macaroni GAA MOSFETs

et al. 2020

Self Cite

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In this paper, we compare quantitatively the results obtained from the numerical simulation of current transport in polysilicon-channel MOSFETs under different modeling assumptions typically adopted to reproduce the basic physics of the devices, including the effective medium approximation and the description of polysilicon as the haphazard ensemble of monocrystalline silicon grains separated by highly defective grain boundaries. In the latter case, both pure drift-diffusion transport and a mix of intra-grain drift-diffusion and inter-grain thermionic emission are considered. Interest is focused on cylindrical nanowire and macaroni gate-all-around structures, due to their relevance in the field of 3-Dimensional NAND Flash memories, focusing not only on the average behavior but also on the variability in the electrical characteristics of the devices.

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“…The data rate of the airborne sensors is usually hundreds of Mb/s or several Gb/s [1,2,3]. This demands onboard data storage system with the high speed, because the data transfer rate of the aerial vehicles' downlink can hardly achieve over 400 Mb/s [4,5,6,7].…”

Section: Introductionmentioning

confidence: 99%

A new technology for real-time file system of high-speed storage system in airborne sensors

Tian

Nie

et al. 2021

IEICE Electron. Express

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The airborne sensors with high data rate demand the onboard high-speed storage system due to the limited bandwidth of the downlinks. The NAND Flash and its products are the most common storage medium, and the conventional FAT file system is widely used in the storage systems. However, there has been a problem in recording the live high-speed data stably with this file system. The management time of the FAT file system is relatively long due to the internal overhead which includes the retrieving and updating of the FAT and FDT. The aim of this study is to investigate the technology for the real-time file system. A technology called FPFPA (FAT post-and FDT post-allocation) method is presented to solve this problem. To evaluate the performance of the proposed method, the management time of the file system using our proposed method is tested on the high-speed storage system of an airborne radar. The result indicates that the proposed method achieves our goal successfully in that the management time of the file system is significantly reduced and sufficiently small.

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Impact of Cycling on Random Telegraph Noise in 3-D NAND Flash Arrays

Cited by 20 publications

References 26 publications

First Evidence of Temporary Read Errors in TLC 3D-NAND Flash Memories Exiting From an Idle State

First Evidence of Temporary Read Errors in TLC 3D-NAND Flash Memories Exiting From an Idle State

A comparison of modeling approaches for current transport in polysilicon-channel nanowire and macaroni GAA MOSFETs

A new technology for real-time file system of high-speed storage system in airborne sensors

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