Impact of D-Flip-Flop Architectures and Designs on Single-Event Upset Induced by Heavy Ions

Abstract

This work highlights the impact of design on the single event upset (SEU) sensitivity of D-Flip-Flops used in a readout circuit (ROIC) under heavy ions. New experimental data obtained at University of Louvain for several designs are presented. The SEE prediction tool MUSCA SEP3 is used to investigate the failure occurrences at the circuit level as a function of the design. In some cases, design specificities allow for increasing in the SEU robustness of the DFF. However, it appeared that cryogenic temperatures limit the impact of the design on the SEU sensitivity of DFFs. The results show a very limited impact of the temperature on the SEU occurrence, independent of the layout. These results are consistent with experimental data presented in recent works regarding SET and SEFI. These results allow for performing irradiation tests of CMOS IR detector (ROIC) at room temperature instead of cooling down the device during the SEE measurements.

Update of Single Event Effects Radiation Hardness Assurance of Readout Integrated Circuit of Infrared Image Sensors at Cryogenic Temperature

“…During all the irradiation test campaigns, the temperature of chips was monitored and regulated by a cryostat which allows temperatures up to 50 K. In order to detect Single Event Latchup (SEL) and to prevent the destruction of the chip, a GUARD (Graphical Universal Autorange Delatcher) system (developed by TRAD, Labège, France) was used on the DUT’s power [ 11 ]. The global views of the experimental setups used during this irradiation campaign are shown in Figure 1 .…”

“…The six DFF chains are composed of 200 cells in order to maximize the SET capture during the irradiation tests as depicted in Figure 2 . The differences between each DFF chain correspond to designs of function tweak, as described in previous work [ 11 ]. In order to minimize the impact of SEU on the clock tree, each of the DFF chains shares several signals, such as: Clock, Reset, Data input and Enable.…”

“…The differences in DFF architecture are based on differences in terms of functions, and multiple data inputs. The full description of DFF designs are presented in a previous work [ 11 ]. In this work, the impact of the temperature is presented on two designs of DFF.…”

SEFI Modeling in Readout Integrated Circuit Induced by Heavy Ions at Cryogenic Temperatures

“…5 (a) presents the SET cross section of a reference of AND gates as a function of LET of heavy ions simulated at 57 K. As expected for the SET, the saturation of the cross section is not well observed. The phenomenon is due to the low drive current for this design of the AND gate [17]. Fig.…”

“…These cell families correspond to the majority area of the digital part of the ROIC. It was revealed that the standard cells of the PDK (Process Design Kit) used by Sofradir for their ROIC have a very similar SET/SEU cross sections for various design in each digital function, especially at cryogenic temperatures (57 K) [4] [17]. According to these works, a hypothesis of a variation of +/-25% of SET/SEU cross section would be considered for each main family of standard cells.…”