“…Figure 3 shows the output power variation experienced during the 24 h stress test vs. the operating output power level. At first, it can be clearly seen when comparing devices from wafer A, B and D that the introduction of the field-plate both improves device reliability, lower output power variation, and device output power operating levels [6,7]. As an example, devices A0, i.e., from wafer A and FP0 structure, experienced a −0.55 dBm variation when operated at a 2.8 W·mm −1 while power variations and operating level were −0.3 dBm and 3.5 W·mm −1 for devices A1 and −0.05 dBm and 5.5 W·mm −1 for devices A2.…”