Impact of Fin Width on Tri-Gate GaN MOSHEMTs

Abstract

In this paper, we present a detailed investiga-1 tion of the impact of fin width (w fin) on tri-gate AlGaN/GaN 2 metal-oxide-semiconductor high electron mobility transis-3 tors (MOSHEMTs). As w fin is reduced, the threshold volt-4 age (V TH) increases, which is due to the enhanced gate 5 control (especially for w fin < 200 nm) thanks to the 3-D 6 geometry of the tri-gate, and the reduced carrier concen-7 tration (N s) caused by a more pronounced strain relax-8 ation and sidewall depletion, as explored using Hall and 9 capacitance-voltage (C-V) measurements. The normally-10 OFF operation was achieved for w fin close to the sidewall 11 depletion width (w dep) of 19.5 nm, since the fin is depleted 12 from its two sidewalls. The impact of w fin on ON-resistance 13 (R ON) and current capability (I D,max) was also investigated, 14 along with the influence of the effective source injection, 15 the trench conduction and the filling factor (FF) on these 16 key characteristics. The degradation caused by the tri-gate 17 fin etching could be fully recovered by increasing the FF. 18 Finally, we show that the tri-gate can reduce gate capac-19 itance (C G) and charge (Q G) in normally-ON MOSHEMTs, 20 depending on the design of the tri-gate and the gate voltage 21 (V G), leading to a smaller R ON • Q G product that is benefi-22 cial for high-frequency switching applications. The results 23 in this paper offer insights into important phenomena in 24 tri-gate GaN devices and are fundamental for the further 25 advance of this technology. 26 Index Terms-Drain current, fin width, GaN, gate capaci-27 tance, threshold voltage, tri-gate. 28 I. INTRODUCTION 29 T RI-GATE technologies have recently attracted consider-30 able attention for lateral GaN electronic devices [1]-[20], 31 thanks to many advantages over conventional planar gates. 32 First, the V TH in tri-gate GaN metal-oxide-semiconductor 33 high electron mobility transistors (MOSHEMTs) increases 34 as w fin decreases, hence, the normally-OFF operation can be 35

High-Frequency GaN-on-Si power integrated circuits based on Tri-Anode SBDs

“…While this sequence is consistent for all the architectures considered, the capacitance value and the position of the steps strongly depend on the device design. In particular, as the nanowire width is reduced, the Tri-Gate and Tri-Anode turn-on shifts closer to 0 V, as a result of the variation in the nanowire threshold voltage [17]- [19]. Additionally, while the capacitance per each nanowire indeed increases due to the 3D structure, leading to a better control as shown by the excellent Tri-Anode blocking performance, the overall device capacitance decreases.…”

Strain relaxation and self-heating effects of fin AlGaN/GaN HEMTs

“…As shown in figure 11(a), V th of fin HEMTs has a positive shift caused by LGC and a further positive shift caused by the strain relaxation. Literatures have reported on this aspect experimentally, but lacking a quantitative analysis on the mechanism [27,33]. For fin HEMTs both the strain relaxation and LGC decrease I DS , while the suppression of self-heating by the trenches increases I DS .…”

“…In the simulations, the device structures (including the gate structure and heterostructure), bias conditions, and the device geometries were set as same as those in the cited literatures. W f and S f were determined by W f /(S f + W f ) = 0.4 in [27] and W f /(S f + W f ) = 0.5 in [33]. The planar HEMTs are considered equivalent to fin HEMETs with W f approaching infinity in which edge effects have negligible impacts.…”

AlGaN/GaN-Based Laterally Gated High-Electron-Mobility Transistors With Optimized Linearity

“…2). In JFET devices, the intrinsic transconductance increases with the gate voltage as in (1), while it is steady after the threshold in HEMT structures [32], [36].…”

“…Although previous works show the effects of gate parameters on device performance in tri-gate and metaloxide-semiconductor HEMT (MOSHEMT) devices [15]- [17], [27], [28], [31], [32], the effect of the gate dimensions on R S and the linearity of laterally gated devices are not studied experimentally in detail in earlier works.…”