In this work, highly linear AlGaN/GaN laterally gated (or buried gate) high-electron-mobility transistors (HEMTs) are reported. The effect of gate dimensions on source-access resistance and the linearity of laterally gated devices are investigated experimentally in detail for the first time. Transistors with different gate dimensions and conventional planar devices are fabricated using two-step electron beam lithography (EBL). Current-voltage, source-access resistance, small-signal, and two-tone measurements are performed to evaluate the linearity of devices. Contrary to conventional planar HEMTs, the intrinsic transconductance of laterally gated devices monotonically increases with increasing gate voltage, showing a similar behavior as junction field-effect transistors (FETs).The source-access resistance shows a polynomial increase with the drain current, which can be reduced by decreasing the filling ratio of the buried gates. Through the optimization of these two competing factors, i.e., intrinsic transconductance and the source-access resistance, flat transconductance with high linearity is achieved experimentally. The laterally gated structure shows flat transconductance and small-signal power gain over a larger span of gate voltage that is 2.5 times higher than a planar device. Moreover, 6.9-dB improvement in output intercept point (OIP3)/P DC is

In this paper, we present a highly robust GaN-based X-band low-noise amplifier (LNA) showing promising small-signal and noise performance as well as good linearity. The LNA is fabricated using in-house 0.15 μm AlGaN/GaN on a SiC HEMT process. Owing to the optimum choice of HEMT topologies and simultaneous matching technique, LNA achieves a noise figure better than 2 dB, output power at 1 dB gain compression higher than 19 dB, input and output reflection coefficients better than À9 and À11 dB, respectively. The small-signal gain of LNA is more than 19 dB for the whole band, and NF has a minimum of 1.74 dB at 10.2 GHz. LNA obtains an OIP3 up to 34.2 dBm and survives input power as high as 42 dBm. Survivability is investigated in terms of gain compression and forward gate current. Reverse recovery time (RRT), a crucial parameter for radar front-ends, is explored with respect to the RC time constant and trap phenomenon. The analysis shows that the significant contribution in RRT is due to traps while the RC time constant is in the nanoseconds range. Moreover, this study also addresses the requirement and choice of a DC gate feed resistor for the subsequent stages in a multi-stage design. The size of the designed LNA chip is 3 mm  1.2 mm only.

High electron mobility transistors (HEMTs) based on gallium nitride (GaN) with a wide range of application potentials need to be rigorously examined for reliability to take advantage of their intrinsically extraordinary properties. The most vital parameter of the reliability, the hotspot, or Tmax, resides in the two-dimensional electron gas (2DEG) temperature profile inside the device where optical access is often restricted. The device surface temperature can be measured by widespread IR thermography with the limitation of diffraction-based IR transmission losses. However, Tmax on the sub-surface cannot be reached thermographically. Although finite element analysis (FEA)-based thermal simulations can easily reveal the 2DEG temperature profile, accuracy is tightly dependent on the realistic modeling of material/structure parameters. Because these parameters are rather sensitive to fabrication and processing, it is quite difficult to specify them accurately. To overcome these drawbacks, a method integrating both IR thermography and FEA thermal analysis is demonstrated on a fabricated high-power 40 × 360  μm packaged GaN HEMT as a proof-of-concept. Utilizing the simulation and measurement temperature profiles, a correlation algorithm is developed so that accuracy of the FEA thermal simulation is improved by calibrating the parameters specific to fabrication/process conditions by thermographic measurement. Then, it is quantitatively shown that the proposed method is able to find the 2DEG temperature profile and Tmax with an accuracy that best suits the intrinsic and extrinsic characteristics of the device under test. The method sheds light on GaN reliability engineering by providing a feasible and reliable alternative to realistically reveal hotspot information for device lifetime assessments.

Source degenerated HEMTs are used to achieve good noise matching and better input return loss without degrading the noise figure and reducing the stability. This work presents an MMIC design for the frequency band of 8 -11 GHz by using HEMTs with source degeneration in 0.15 μm GaN on SiC technology. All design work is done in the Advanced Design System. The LNA delivers more than 6.9 dB gain with better than 8.5 dB and 9.5 dB input and output return losses, respectively. In addition, the gain ripple is around 2.7 dB. The noise figure of the amplifier is achieved below 1.1 dB with P1dB of 17.2 dBm and %12.7 drain efficiency within the operating bandwidth at the bias conditions of 9 V/20 mA.

GaAs and SiGe technologies take an edge over GaN-based devices in terms of better noise figure (NF). In this article, we present HEMT topologies and design techniques to achieve a sub-1.2 dB NF for a GaN-based X-band lownoise amplifier (LNA). This NF is comparable with state-of-the-art reported works in competitive GaAs and SiGe technologies. Moreover, this is the best reported NF in X-band using GaN technology to date. Two LNAs are fabricated using in-house 0.15 μm AlGaN/GaN on the SiC HEMT process. LNA-1 has inductive source degenerated (ISD) HEMTs at both stages, while LNA-2 has ISD HEMT at the first and common source at the second stage. The significance of ISD HEMT, for the first or subsequent stages in a multi-stage design, towards NF improvement is addressed. The criticality of stability networks towards NF contribution and its design is discussed in detail. Furthermore, even-mode stability of each HEMT after complete LNA design is assured using the S-probe method in Pathwave Advanced Design Systems.