Impact of Gate Tunneling Leakage on Performances of Phase Locked Loop Circuit in Nanoscale CMOS Technology

Abstract

The influence of gate tunneling leakage on the circuit performances of phase locked loop (PLL) in nanoscale CMOS technology has been investigated by simulation. The basic PLL with second-order loop filter is used to simulate the impact of gate tunneling leakage on performance degradation of PLL in a standard 90-nm CMOS process. The MOS capacitors with different oxide thicknesses are used to investigate this impact to PLL. The locked time, static phase error, and jitter of second-order PLL are degraded by the gate tunneling leakage of MOS capacitor in loop filter.

Prediction of reference spur in frequency synthesisers

“…In sub‐micron technology leakage is a big concern. Area effective realisation of the loop filter using MOS capacitor also provides significant leakage at the VCO input node [20, 21]. Therefore, for subsequent analysis, the triangular approximation of the ripple which exists because of the leakage at VCO input node, has been used.…”