Impact of mutual inductance on timing in nano-scale SoC

Abstract

This paper investigates the impact of mutual inductance (M ) on interconnect signal delay estimation according to resistance (R), inductance(L), and capacitance(C) in nano-scale system on a chip (SoC), suggesting a method to predict and suppress the impact. The proposed methodology first calculates the difference in delay between RLC and RLM C wire models for a set of parameter variations, then builds response surface functions (RSF) using physical parameters including wire width and spacing. The proposed method contributes to the following actions. 1) Describe design rules to avoid mutual inductance effects. 2) Select wires which require RLM C models for delay estimation 3) Correct the estimated delay when using an RLC model. As an example, situations to limit the mutual inductance effect is shown as to a 14nm technology node.