Integration schemes of bulk FinFET SRAM cell with bulk planar FET peripheral circuit are studied for the first time. Two types of SRAM cells with different β-ratio were fabricated and investigated in the view of static noise margin (SNM). High SNM of 122 mV is obtained in the cell with 15 nm Fin width, 90 nm channel height and 20 nm gate length at V dd = 0.6 V. This is the smallest gate length FinFET SRAM reported to date.A higher beta ratio (β > 2.0) in FinFET SRAM cell will be also achieved by tuning the effective channel width of each FinFETs without area penalty by taking advantage of bulk-Si substrate.

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A methodology of including MOSFET characteristics fluctuation into BSIM3v3 SPICE model is proposed. Fundamentally physical parameters such as gate oxide thickness fl0Q channel concentration (NCH), gate length (L), parasitic resistance (RDSW)are chosen as an independent parameter set. Parameters which should be expressed by the above set are described in simple physical equations. This method allows not only statistical simulation based on electric test data that can be easily measured nlth full-auto tester system, but also characteristics prediction of modified device structure or of future technoIogy devices.

In this paper, a new gate structure, W/WNx/PolySi, was proposed as the breakthrough of serious parasitic caused by RC delay of gate electrode in down scaled CMOS devices. The MOSFETs with the gate electrode structure were fabricated combined with a deep submicron CMOS process. As a result, 1.652/0 gate sheet resistance without its increase in fine line gate was obtained. Moreover, it was demonstrated that the thin WNx layer formed by reactive sputtering can be an excellent barrier layer from the gate oxide integrity and W/Poly-Si contact resistivity point of view.