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Two-step recessed SiGe-S/D pMOSFET [1] has been optimized with a combination of compressive stress liner. Optimization on source and drain overlap, defect control and elevated SiGe-S/D structure are discussed experimentally. As a result of the careful optimization, record high drive current of 714 �A/�m at Vdd=1.0V, Ioff =100 nA/�m at 24 nm gate length, is demonstrated.

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For the first time, we demonstrate standard cell gate density of 3650 KGate/mm 2 and SRAM cell of 0.124 μm 2 for 32nm CMOS platform technology. Both advanced single exposure (SE) lithography and gate-first metal gate/high-k (MG/HK) process contribute to reduce total cost per function by 50% from 45nm technology node, which is unattainable by dual exposure (DE) lithography or double patterning (DP) and poly/SiON gate stack.