Impact of negative bias temperature instability on digital circuit reliability

Reddy, V.; Krishnan, A.T.; Marshall, Andrew; Rodríguez, J. A.; Natarajan, S.; Rost, T.A.; Krishnan, S.

doi:10.1109/relphy.2002.996644

Cited by 140 publications

(50 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In order to obtain V IL , V OH the LEVEL1 nFET drain current in saturation region [4] and pFET drain current in triode region [5] has been equalized (4) …”

Section: Appendix Amentioning

confidence: 99%

See 1 more Smart Citation

Modelling and experimental verification of the impact of negative bias temperature instability on CMOS inverter

Berbel

Fernández

Gil

2009

Microelectronics Reliability

View full text Add to dashboard Cite

The effects of negative bias temperature instability (NBTI) on the performance of a CMOS inverter have been investigated by means of both simulation and experimental methods. The simulation of NBTI effects on CMOS inverter has been done by shifting the pFET V tho BSIM parameter. The results show that NBTI shifts the inverter transfer curve, reduces the low noise margin and current consumption but increases the high noise margin. A good agreement between simulation and experimental results has been obtained. Therefore, it can be assumed that the effect of NBTI on CMOS circuits can be mainly predicted by shifting the V tho pFET parameter.

show abstract

“…In order to obtain V IL , V OH the LEVEL1 nFET drain current in saturation region [4] and pFET drain current in triode region [5] has been equalized (4) …”

Section: Appendix Amentioning

confidence: 99%

“…At circuit level, the NBTI effects have not been deeply investigated. However, some works have pointed out that NBTI provoke a signal noise margin (SNM) reduction on SRAM cell [4] and a frequency reduction in case of CMOS ring oscillator [5].…”

Section: Introductionmentioning

confidence: 99%

Modelling and experimental verification of the impact of negative bias temperature instability on CMOS inverter

Berbel

Fernández

Gil

2009

Microelectronics Reliability

View full text Add to dashboard Cite

show abstract

“…A corresponding and dual effect, known as Positive Bias Temperature Instability (PBTI) can be seen for NMOS devices. Although PBTI causes less degradation than NBTI 72) , it is becoming increasingly important in its own right. Under DC stress, the threshold voltage of a PMOS transistor degrades with time, t, at a rate given by…”

Section: Bias Temperature Instabilitymentioning

confidence: 99%

Variability and Statistical Design

Sapatnekar

2008

IPSJ Transactions on System LSI Design Methodology

View full text Add to dashboard Cite

With each technology generation, the effects of on-chip variations are seen to more profoundly affect digital circuit behavior. These variations may arise from fluctuations attributed to the manufacturing process (e.g., drifts in channel length, oxide thickness, threshold voltage, or doping concentration), which affect the circuit yield, as well as variations in the environmental operating conditions (e.g., supply voltage or temperature) after the circuit is manufactured, which impact the performance of the design. These effects can cause unacceptable alterations in circuit performance parameters such as timing and power, and variation-tolerant design is imperative for next-generation designs. This paper overviews research in this area, describing methods for the analysis and optimization of statistical effects.

show abstract

“…NBTI is the aging effect that decreases PMOS current mainly due to shift over the silicon lifetime [10], [11]. This shift is strongly dependent on gate-source bias and temperature but barely dependent on drain voltage.…”

Section: B Nbtimentioning

confidence: 99%

A dual-core 64-bit ultraSPARC microprocessor for dense server applications

Takayanagi

Shin

Petrick

et al. 2005

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

Abstract-A dual-core 64-bit microprocessor optimized for compute-dense systems such as rack-mount and blade servers for network computing was developed. The chip consists of two Ultra-SPARC II cores, each with its own 512 kB L2 cache, a DDR-1 memory controller, and symmetric multiprocessor bus (JBus) controllers. The 206-mm 2 die is fabricated in 0.13-m CMOS technology with seven layers of Cu and a low-k dielectric. The chip offers a highly efficient performance-per-watt ratio with a typical power dissipation of 23 W at 1.3 V and 1.2 GHz. A short design cycle was achieved by leveraging existing designs wherever possible and developing effective design methodologies and flows. Significant design challenges faced by this project are described. These include deep-submicron design issues, such as negative bias temperature instability (NBTI), leakage, coupling noise, intra-die process variation, and electromigration (EM). A second important design challenge was implementing a high-performance L2 cache subsystem with a short four-cycle core-to-L2 latency including ECC.Index Terms-Chip Multithreading (CMT), coupling noise, current-mode sense amplifier, deep-submicron technology, dense server, dual-core, ECC, electromigration, hold time, leakage, L2 Cache, microprocessor, multicore, multiprocessor, multithread, negative bias temperature instability (NBTI), process variation, thread-level parallelism (TLP), translation look aside buffer (TLB), UltraSPARC.

show abstract

Impact of negative bias temperature instability on digital circuit reliability

Cited by 140 publications

References 11 publications

Modelling and experimental verification of the impact of negative bias temperature instability on CMOS inverter

Modelling and experimental verification of the impact of negative bias temperature instability on CMOS inverter

Variability and Statistical Design

A dual-core 64-bit ultraSPARC microprocessor for dense server applications

Contact Info

Product

Resources

About