1995
DOI: 10.1063/1.359209
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Impact of oxygen related extended defects on silicon diode characteristics

Abstract: The electrical activity of extended lattice defects formed by interstitial oxygen precipitation in silicon is studied. Their impact on diode characteristics and on minority carrier lifetime is addressed for different initial oxygen contents and pretreatments. The carrier traps present in the substrate are studied with deep level transient spectroscopy and with photoluminescence spectroscopy. The obtained electrical results are correlated with those of structural and chemical characterization using cross-sectio… Show more

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Cited by 88 publications
(76 citation statements)
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“…The perimeter (J P ) and area (J A ) leakage current components have been extracted at fixed reverse bias from the slope and intercept of the reverse current density J R versus P/A ratio plot, given by (1) [6][7][8]. This approach is valid when corner and parasitic components can be neglected.…”
mentioning
confidence: 99%
“…The perimeter (J P ) and area (J A ) leakage current components have been extracted at fixed reverse bias from the slope and intercept of the reverse current density J R versus P/A ratio plot, given by (1) [6][7][8]. This approach is valid when corner and parasitic components can be neglected.…”
mentioning
confidence: 99%
“…It is well-established that DLTS reveals two electron traps in p-type material at about 0.43 and 0.21 eV below the bottom of the conduction band in high-oxygen Cz material. 8 However, taking into account that typical emission rate windows are in the range of 1-100 ms, this is clearly much too fast to explain the observed slow current transients. It should be remarked here that in the range 77-300 K no DLTS levels were found in the diodes under study.…”
Section: Current Transients In Almost-ideal Czochralski Silicon P -N mentioning
confidence: 97%
“…It is certainly in the range of oxide precipitate sizes observed by transmission electron microscopy. 8 A final remark should be made related to the spatial location of the responsible defects. Since the Cz wafers have been internally gettered, it is expected that a defect-lean zone of around 10-20 m forms.…”
Section: Current Transients In Almost-ideal Czochralski Silicon P -N mentioning
confidence: 99%
“…It is known that large oxide precipitates degrade the gate oxide integrity [16][17][18]. Microdefects generally decrease the minority carrier lifetime and can cause leakage currents in devices [19,20]. Defects in the active area of the device are harmful to the deep trenches of memory cells.…”
Section: Introductionmentioning
confidence: 99%