Impact of parameter variations on FinFET faults

Harutyunyan, G.; Tshagharyan, G.; Zorian, Y.

doi:10.1109/vts.2015.7116276

Cited by 9 publications

(3 citation statements)

References 5 publications

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“…[10] proposed a new strategy for modeling FinFET-specific faults, and static faults are considered to test typical faults of FinFET and planar memory. [11] investigated the parameter variation impact on FinFET-specific fault module and coverage. [3][12][13] [14] studied the effect of resistive defects on the behavior of FinFET memory and obtained the corresponding functional fault model through experiments.…”

Section: Finfet Functional Fault Modelmentioning

confidence: 99%

A new march test for FinFET memory functional fault detection

Wang

Huang

Cai

et al. 2023

2022 Workshop on Electronics Communication Engineering

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FinFET (Fin Field-Effect Transistor) technology is widely used in advanced transistor manufacturing process due to its lower leakage current, smaller short-channel effect, and lower power consumption. However, this special physical structure is very susceptible to manufacturing defects, which makes the FinFET memory prone to functional faults. Therefore, an efficient fault detection method is very important for the defect detection of FinFET memory. A detection algorithm called March FRD for FinFET memory faults is proposed in this paper. This paper summarizes the FinFET functional fault model, analyzes the corresponding coverage conditions, and verifies the correctness of the algorithm. March FRD performs well in detecting resistance dynamic faults, and its total fault coverage reaches 91.7%, which is significantly better than other existing March tests.

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Section: Finfet Functional Fault Modelmentioning

confidence: 99%

A new march test for FinFET memory functional fault detection

Wang

Huang

Cai

et al. 2023

2022 Workshop on Electronics Communication Engineering

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show abstract

“…Refence [12] proposed a fault modeling strategy, and considered that FinFET memory also has various functional faults of flat memory. Refence [13] studied the influence of parameter changes such as temperature, voltage, and current on functional faults of FinFET memory. Refence [14][15] [16] studied the effect of resistive defects on the behavior of FinFET memory, obtained the corresponding functional fault model through experiments, and found that there are two or more read operations in dRDF and dDRDF when FinFET memory is affected by resistive defects.…”

Section: Finfet Memory Functional Fault Modelmentioning

confidence: 99%

A Built-In Self-Test Circuit Based on March FRDD Algorithm for FinFET Memory

Wang,

Huang,

Cai

et al. 2023

Advances in Transdisciplinary Engineering

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FinFET memory is widely used in various semiconductor products due to its good read/write margin, lower power consumption, and faster driving speed. However, the forked 3D physical structure and the increased density of storage are very susceptible to manufacturing defects, which may cause memory functional logic faults that are different from traditional planar CMOS memories. Therefore, it is critical to explore an effective test method for FinFET memories. This paper proposes a MBIST circuit for detecting functional faults of FinFET memory. The proposed circuit is based on the March FRDD algorithm and performs well in detecting resistance dynamic faults. The area of this circuit is 85.3286 µm2, which benefits from the design method of multiplexing the internal part of the circuit. The total fault coverage of the MBIST circuit reaches 91.7%, which provides great convenience for FinFET memory testing.

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“…Testing and bridging of delay faults becomes critical by scaling of the technology. In presence of defects the behaviour of FinFET INV and NAND gates examined 7 .…”

Section: Introductionmentioning

confidence: 99%

Testing and Diagnosis of Delay Faults in Finfet VLSI Circuits using Non-Incremental Genetic Algorithm

Rayudu*,

Jahagirdar,

Rao

2019

IJITEE

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FinFet transistors are used in major semiconductor organizations which play a significant role in the development of the silicon industries. Due to few embedded memories and other circuit issues the transistors have specific faults in manufacturing, designing of the circuit etc. This paper presents an advanced test algorithm to diagnose those faults. The circuit with different gates is designed to identify the places having faults. In addition, algorithms such as non-incremental algorithms is used to find critical path, path delay and PDF of Critical path delay and Genetic Algorithm for optimisation of Critical path delay for sensitive test vector and no of iterations. The transfer characteristics curve is plotted along with the delay curve which helps in finding out the simulation parameters such as noise margin, propagation delay. The results in the methodology calculate the probability density function of the critical path by estimating mean, standard deviation and variance. The advantages of the integration of the two algorithms in this paper help in analyzing the specific faults in the circuits and the error correction of the broken link in the path analysis and has enhanced performance. Furthermore, more complicated circuits are analyzed for fault detection with different approach. In this paper the research work on testing, diagnosis, estimation of Critical path and PDF of Critical path delay faults for FinFET based Combinational Circuits for 20nm and 32 nm Technologies are presented for the first time using latest Non Incremental Genetic algorithm.

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Impact of parameter variations on FinFET faults

Cited by 9 publications

References 5 publications

A new march test for FinFET memory functional fault detection

A new march test for FinFET memory functional fault detection

A Built-In Self-Test Circuit Based on March FRDD Algorithm for FinFET Memory

Testing and Diagnosis of Delay Faults in Finfet VLSI Circuits using Non-Incremental Genetic Algorithm

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