Impact of plasma induced damage on PMOSFETs Tin/HF silicate stack

Song, Seung-Chul; Bae, S.H.; Zhang, Z.; Sim, J.H.; Sassman, B.; Bersuker, G.; Zeitzoff, P.; Lee, B.H.

doi:10.1109/relphy.2005.1493119

Cited by 12 publications

(8 citation statements)

References 11 publications

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“…15) There have been many reports on PCD to high-k MOSFETs. [15][16][17][18][19] The damage is usually quantified by measuring the gate leakage current increase 16,17) and threshold voltage shift (ÁV th ). 15,19) Since this charging damage is considered to be inevitable in present-day plasma equipment, antenna design rules that limit the maximum antenna ratio in circuits [20][21][22] and protection diode schemes 13,14,20,[23][24][25][26] have been introduced to minimize the damage.…”

Section: Introductionmentioning

confidence: 99%

Analytic Model of Threshold Voltage Variation Induced by Plasma Charging Damage in High-k Metal–Oxide–Semiconductor Field-Effect Transistor

Eriguchi

Kamei

Takao

et al. 2011

Jpn. J. Appl. Phys.

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We discuss plasma charging damage (PCD) to high-k gate dielectrics and the resultant threshold voltage shift (ΔV th) in n-channel metal–oxide–semiconductor field-effect transistors (n-ch MOSFETs). The PCD induced by the antenna effect is focused on, and ΔV th and its variation are estimated for MOSFETs treated by various plasma processes. We propose a ΔV th variation model based on both the power-law dependence of ΔV th on the antenna ratio r (= exposed metal interconnect area/gate area) and the r distribution deduced from an interconnect-length distribution function (ILDF) in a large-scale integrated (LSI) circuit. Then, we simulate the variations in ΔV th [σ(ΔV th)] and the subthreshold leakage current I off [σ(I off)], in accordance with the employed r distribution. The model prediction quantitatively shows the effects of PCD on σ(ΔV th) and σ(I off): The antenna effect is found to increase σ(ΔV th) and σ(I off).

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Section: Introductionmentioning

confidence: 99%

Analytic Model of Threshold Voltage Variation Induced by Plasma Charging Damage in High-k Metal–Oxide–Semiconductor Field-Effect Transistor

Eriguchi

Kamei

Takao

et al. 2011

Jpn. J. Appl. Phys.

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“…However, the introduction of high-K dielectrics, which are supposed to replace SiO2, again raises concerns about their susceptibility to plasma-induced charging [3][4][5]. The complexity of high-K gate stack integration in conjunction with metal electrodes poses additional challenges since the effects of plasma-induced damage from the novel processes may not yet be known [3].…”

Section: Introductionmentioning

confidence: 99%

Comparison of Plasma-Induced Damage in SIO2/TIN and HFO2/TIN Gate Stacks

Young¹,

Bersuker²,

Zhu

et al. 2007

2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual

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SiO2 and HfO2 gate dielectrics with TiN electrodes were subjected to an aggressive post-fabrication plasma exposure. A comparison of plate and comb antenna structures before and after exposure demonstrated that the plate antennae structures demonstrate evidence of plasma-induced damage while the comb structures did not. The physical origin of PD in SiO2 devices was found to be the amphoteric interface states, while the primary effect in HfO2 devices was charges trapped in the bulk of the high-K film.

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“…The occurrence of additional gate dielectric leakage implies the existence of additional current paths within the gate dielectric layers. Prior to conductive path formation within the dielectric layers, sufficient damage (i.e., traps and defects) accumulates to influence the initial V TH [13] and DV TH shifts after electrical stress [22]. Further, damaged transistors with a large antenna ratio have a significant difference in initial V TH and simultaneously depict great influence on DV TH shift after BTI stress compared with undamaged transistors.…”

Section: Bti Instability and Silc Increasementioning

confidence: 99%

“…Paying significant attention to the PID-enhanced transistor reliability degradation is necessary as CMOS technology continues to scale. Previous studies show the PID impacts high-k/metal-gate transistors [13,14]. However, a comprehensive study for comparing the PID effects between SiO 2 /poly-gate and high-k/metal-gate transistors on the antenna ratio dependence and gate dielectric thickness dependence in terms of damage-enhanced gate dielectric failure and damage-enhanced transistor reliability degradation is still lacking.…”

Section: Introductionmentioning

confidence: 99%