Impact of Post-Oxidation Annealing on Low-Frequency Noise, Threshold Voltage, and Subthreshold Swing of p-Channel MOSFETs

Abstract

The impact of post-oxidation annealing on the low-frequency noise, threshold voltage, and subthreshold swing of p-channel MOSFET is reported. The low-frequency noise is improved significantly with post-oxidation annealing and a modest and S reduction is observed. Oxide traps are primarily extracted from measured noise. They are also extracted from threshold voltage and subthreshold slope shift. The contribution of oxide traps to threshold voltage shift and 1 noise is analyzed through quantitative approach in the light of correlated fluctuation theory. Analysis on experimental results shed light on the well-known controversy about the origin of low-frequency noise, suggesting that experimental results are in agreement with mobility fluctuation theory whereas correlated number fluctuation theory explains the result assuming only a fraction of total oxide charge at a given energy level participates in the generation of low-frequency noise.

Low Operating Voltage Single ZnO Nanowire Field-Effect Transistors Enabled by Self-Assembled Organic Gate Nanodielectrics

“…High subthreshold slopes are usually due to either the existence of surface trap states, leakage current components that are not exponentially dependent on V gs , or incomplete gating effects due to the cylindrical geometry of the nanowire. In conventional metal−oxide−semiconductor FETs, it has been shown that surface treatments on the SiO 2 gate insulator, including HF, application of a plasma, hydrogenation, or annealing in N 2 and H 2 can reduce the density of interface traps and mobile charges and improve the subthreshold slope. , To investigate the off-current and subthreshold behavior, SAS-based ZnO NW-FETs were exposed to 2-min ozone treatments, which are thought to increase the doping density via creation of oxygen vacancies − and may reduce surface trap charge densities. The UV light used to generate the ozone was shielded to prevent possible degradation of the SAS.…”

Experimental characterization of low-frequency noise in power MOSFETs for defectiveness modelling and technology assessment

“…Typical values of the trap density in SiO2 dielectric are available in the literature for the CMOS technology [21][22][23], and they can be compared with our findings in power U-MOSFETs (i.e., around 10 16 cm -3 eV -1 ). In [21] a trap density of 4.3•10 16 cm -3 eV -1 is found for p-MOSFETs having a gate oxide thickness of 2.2 nm.…”

“…In [21] a trap density of 4.3•10 16 cm -3 eV -1 is found for p-MOSFETs having a gate oxide thickness of 2.2 nm. In [22] the trap density varies between 5•10 16 cm -3 eV -1 and 2.5•10 17 cm -3 eV -1 , depending on the annealing conditions of oxide with thickness of 3.3 nm. In [23] the trap density, in the case of gate oxide thickness of 7-8 nm, varies between 3•10 16 cm -3 eV -1 and 10 17 cm -3 eV -1 .…”

Degradation of 1/f noise in short channel MOSFETs due to halo angle induced VT non-uniformity and extra trap states at interface

“…Fig. 3 suggests a 2.5 mV/decade degradation in sub threshold slope for higher tilt angle from which the interfacial charge density (D it ) can be extracted by using DS = (kT/q) ln10(DQ it / C ox ) [12]. Fig.…”