In this paper, we present the results of an experimental analysis of the degradation induced by negative bias temperature stress (NBTS) in trench-gated p-channel power MOSFETs. Threshold voltage and carrier mobility are affected by holes trapping in bulk oxide and interface states generation due to oxide electric field effects. A fast recovery phase occurs when gate bias is removed or reduced in order to measure the threshold voltage. Hence, various techniques for evaluating threshold voltage shift are adopted in order to highlight the differences in the dynamics of degradation. We investigate the influence of gate bias level during the stress. Moreover, with the help of recovery studies, we try to distinguish the impact of interface states generation and charge trapping on the NBTS degradation.

In this paper, we present a combined measurement/simulation method, implemented in order to estimate the spatial and energy oxide trap distribution induced by negative bias temperature instability (NBTI) stress in p-channel power U-MOSFETs. The methodology consists in analyzing the recovery phase at different bias conditions and correlating the results with TCAD numerical simulations. We found an oxide trap distribution positioned between 2.24 and 3.04 nm distant from oxide/channel interface with an energy level confined in the silicon bandgap

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In this paper we analyze LF noise in trench-gate power MOSFETs to investigate the effect of negative bias temperature stress on the gate dielectric quality. We study how the amount of stress time influences both the threshold voltage and the trap density within gate oxide. After the stress, recovery conditions are applied to the device and its properties, in terms of threshold voltage, on-current and trap density, are analyzed. The present study allows to identify permanent and recoverable mechanisms associated to the applied stress

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