Impact of power density limitation in gigascale integration for the SIMD pixel processor

Chai, Sek; Gentile, Antonio; Wills, D.S.

doi:10.1109/arvlsi.1999.756037

Cited by 6 publications

(14 citation statements)

References 12 publications

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“…A Technology Scenario Analyzer (TeSA) was developed to project the power consumption of the digital components within the focal plane architecture using different fabrication technologies [57]. The power consumption has been projected for fabrication technologies ranging from 250 nm to 100 nm using a 10 MHz clock (Fig.…”

Section: Projected Powermentioning

confidence: 99%

Efficiency Analysis for a Mixed-Signal Focal Plane Processing Architecture

Robinson

Wills

2005

J VLSI Sign Process Syst Sign Image Video Technol

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Abstract. Monolithic integration of photodetectors, analog-to-digital converters, data storage, and digital processing can improve both the performance and the efficiency of future portable image products. However, digitizing and processing a pixel at the detection site presents the design challenge to deliver a system with the required performance at the lowest cost, not just a system with the highest performance. This paper analyzes the area-time efficiency, the area efficiency, and the energy efficiency of a mixed-signal, SIMD focal plane processing architecture that executes front-end image applications with neighborhood processing. Implementations of the focal plane architecture achieve up to 81x higher area efficiency and up to 11x higher energy efficiency when compared to traditional TI DSP chips. Higher efficiency ratings are required to maintain portability while addressing technology limitations such as interconnect wiring density, heat extraction, and battery life. Systems can be implemented with a less expensive fabrication technology by increasing the number of pixels per processing element (PPE).

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Section: Projected Powermentioning

confidence: 99%

Efficiency Analysis for a Mixed-Signal Focal Plane Processing Architecture

Robinson

Wills

2005

J VLSI Sign Process Syst Sign Image Video Technol

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“…Elements in the heterogeneous architecture models are extracted from gate level schematics [26]- [28] and chip layout [29] to capture details on cell organization, circuit placement, and internal routing within a functional unit. The number of logic gates and the number of pins are tabulated in closed-form equations (Table II), as functions of architectural parameters previously shown in Table I.…”

Section: A Model Derivationsmentioning

confidence: 99%

Heterogeneous architecture models for interconnect-motivated system design

Chai

Taha

Wills

et al. 2000

IEEE Trans. VLSI Syst.

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On-chip interconnect demand is becoming the dominant factor in modern processor performance and must be estimated early in the design process. This paper presents a set of heterogeneous architectural models that combines architecture description and Rent's Rule-based wiring models. These architecture models allow flexible heterogeneous system specifications, enabling investigations of prospective designs in different technology scenarios. Comparisons against actual data demonstrate the models' effectiveness for architecture explorations with highly accurate estimations of local and global wiring demand, as well as chip area and cycle time. Simulation of two candidate system designs reveal trends in interconnect delay with increasing architectural complexity, and confirm the need for high computational locality and short global wires for future architectures.

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“…Architecture models in [5] have shown that VLSI technology by the year 2012 supports a SIMPil system with approximately 850K-pixel (920x920). Power consumption for PEs is contained below 50 Watts for a 52,900 processor system in 50nm technology, with a projected performance in excess of 70 Tops/s.…”

Section: Performance Resultsmentioning

confidence: 99%

“…The symbolic layout of the prototype PE is shown in Figure 3. A single PE is estimated to consume about 44.1 mW at 5 V, running at 25MHz over an application workload [5]. Large arrays of SIMPil PEs can be simulated using the SIMPil Simulator, an instruction level simulator, running under Windows95™ [24].…”

Section: Simpil System Architecturementioning

confidence: 99%

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Hyper-spectral image processing applications on the SIMD Pixel Processor for the digital battlefield

Chai

Gentile

Lugo-Beauchamp

et al.

Proceedings IEEE Workshop on Computer Vision Beyond the Visible Spectrum: Methods and Applications (CVBVS'99)

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Future military scenarios will rely on advanced imaging sensor technology beyond the visible spectrum to gain total battlefield awareness. Real-time processing of these data streams requires tremendous computational workloads and I/O throughputs. This paper presents three applications for hyper-spectral data streams, vector quantization, region autofocus, and K-means clustering, on the SIMD Pixel Processor (SIMPil). In SIMPil, an image sensor array (focal plane) is integrated on top of a SIMD computing layer to provide direct coupling between sensors and processors, alleviating I/O bandwidth bottlenecks while maintaining low power consumption and portability. Simulation results with sustained operation throughputs of 500-1500 Gops/sec support real-time performances and promote focal plane processing on SIMPil.

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Impact of power density limitation in gigascale integration for the SIMD pixel processor

Cited by 6 publications

References 12 publications

Efficiency Analysis for a Mixed-Signal Focal Plane Processing Architecture

Efficiency Analysis for a Mixed-Signal Focal Plane Processing Architecture

Heterogeneous architecture models for interconnect-motivated system design

Hyper-spectral image processing applications on the SIMD Pixel Processor for the digital battlefield

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