Impact of Process Fluctuations on RF Small-Signal Parameter of Gate-All-Around Nanosheet Transistor Beyond 3 nm Node

Sun, Yabin; Gao, Hengbin; Li, Xianglong; Yang, Xiaoqiao; Liu, Ziyu; Liu, Yun; Shi, Yanling

doi:10.1109/ted.2021.3130009

Cited by 6 publications

(2 citation statements)

References 35 publications

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“…Gate-all-around (GAA) Silicon (Si) 1 Rajat Butola, Yiming Li, and Sekhar Reddy Kola are with the Parallel and Scientific Computing Laboratory, Electrical Engineering and Computer nanosheet (NS) is such a nanoscale device that is used to produce chips under 5 nm technology node [19][20][21]. Thus, NS is one of the most advanced transistors for device logic applications for future technology nodes [22], [23]. However, due to scaling the devices have become more prone to process variation (PV) and therefore they need to be considered separately in IC designing [24]- [31].…”

Section: Introductionmentioning

confidence: 99%

A Comprehensive Technique Based on Machine Learning for Device and Circuit Modeling of Gate-All-Around Nanosheet Transistors

Butola,

Li,

Kola

2023

IEEE Open J. Nanotechnol.

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Machine learning (ML) is poised to play an important part in advancing the predicting capability in semiconductor device compact modeling domain. One major advantage of ML-based compact modeling is its ability to capture complex relationships and patterns in large datasets. Therefore, in this paper a novel design scheme based on dynamically adaptive neural network (DANN) is proposed to develop fast and accurate compact model (CM). This framework constitutes a powerful yet computationally efficient methodology and exhibits emergent dynamic behaviors. This paper demonstrates that the compact model based on ML can be designed to replicate the performance of conventional compact model for nanodevices. For this work, gate-all-around (GAA) nanosheet (NS) device characteristics are comprehensively analyzed for process variability sources using the proposed model. The device geometry parameters such as channel length, nanosheet width and nanosheet thickness are fed as input features to the DANN model. The adaptive neural network learns dynamically by updating weights of the model in accordance with the input features and achieves accurate neural weight convergence. The proposed model predicted the electrical characteristics of NS devices with less than 1% error rate. The model is also implemented and validated for the simulations of digital circuit designs such as inverter, and logic gates.

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Section: Introductionmentioning

confidence: 99%

A Comprehensive Technique Based on Machine Learning for Device and Circuit Modeling of Gate-All-Around Nanosheet Transistors

Butola,

Li,

Kola

2023

IEEE Open J. Nanotechnol.

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“…When entering millimeter-wave even T-Hz band, the transistors will experience severe parasitic effects [4]. An accurate physically oriented circuit model and parameter extraction technique for a GAA nanosheet transistor are very important to evaluate the fabrication process, optimize the device structure and help in circuit design [5][6][7].…”

Section: Introductionmentioning

confidence: 99%

Sub-THz Small-Signal Equivalent Circuit Model and Parameter Extraction for 3 nm Gate-All-Around Nanosheet Transistor

Sun

Gao

et al. 2022

Processes

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This paper presents a novel RF small-signal equivalent circuit model and parameter extraction for 3 nm nanosheet gate-all-around field effect transistor (GAAFET). The extrinsic parasitic effect induced by ground-signal-ground (GSG) layout is evaluated by 3D full-wave electromagnetic simulation, and an improved five-step analytical parameter extraction method is proposed for such extrinsic GSG layout. The model parameters for the intrinsic device are analytically determined with the help of nonlinear rational function fitting. The accuracy of the proposed extraction method was confirmed via comparisons between device simulator and electromagnetic simulator with frequency responses up to 300 GHz. Excellent agreement is obtained between the simulated and modeled S-parameters, and the calculated error is lower than 2.689% for the extrinsic layout, and 0.897% for the intrinsic device in the whole frequency range among multi-bias points.

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Effect of Process-Induced Variations on Analog Performance of Silicon based Nanosheet Transistor

Pundir

Bisht

Saha

et al. 2023

Silicon

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Impact of Process Fluctuations on RF Small-Signal Parameter of Gate-All-Around Nanosheet Transistor Beyond 3 nm Node

Cited by 6 publications

References 35 publications

A Comprehensive Technique Based on Machine Learning for Device and Circuit Modeling of Gate-All-Around Nanosheet Transistors

A Comprehensive Technique Based on Machine Learning for Device and Circuit Modeling of Gate-All-Around Nanosheet Transistors

Sub-THz Small-Signal Equivalent Circuit Model and Parameter Extraction for 3 nm Gate-All-Around Nanosheet Transistor

Effect of Process-Induced Variations on Analog Performance of Silicon based Nanosheet Transistor

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