Impact of Program/Erase Cycling Interval on the Transconductance Distribution of NAND Flash Memory Devices

Chiu, Yu–Jen; Chang, Kun Chia; Lin, Hsin-Jyun Vincent; Tsai, Hung-Te-En; Lin, Pole-Shang; Li, Hsin-Chiao; Takeshita, Toshiaki; Yano, Masaru; Shirota, R.

doi:10.1109/ted.2020.3024484

Cited by 7 publications

(5 citation statements)

References 27 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…where Q 0 is the saturation value of Q , T C α is the exponential factor, k is the reaction action constant of oxide degradation, and E A G , is the activation energy of oxide damage creation. The values of these parameters could be obtained from the data in 20) under the condition…”

Section: Resultsmentioning

confidence: 99%

See 1 more Smart Citation

The origin of oxide degradation during time interval between program/erase cycles in NAND Flash memory devices

Chiu¹,

Tsai²,

Chang³

et al. 2021

Jpn. J. Appl. Phys.

Self Cite

View full text Add to dashboard Cite

This paper investigates the origin of NAND cell degradation during the time interval (t wait) between program/erase (P/E) cycles. It is observed that, at room temperature, the transconductance reduction is sensitive to from erase-to-program, and longer from erase-to-program results in larger In contrast, has almost no clear dependence on from program-to-erase. Using our previous statistical method, the activation energy ( ) of oxide damage creation is extracted. As the starting voltage ( ) of incremental step pulse programming (ISPP) varied from 14.6 to 17.6 V, has a shift of about 11 meV and 13 meV for both from erase-to-program of 0.1 s and 4 s, respectively. We also found that linearly decreases as the maximum oxide field increases during ISPP. It would be plausible to consider a model in which the program steps generated holes inside the tunneling oxide, which recombined with inversion electrons near Si/SiO2 interface during from erase-to-program. This process generates more trap states and thus results in larger

show abstract

Section: Resultsmentioning

confidence: 99%

“…However, our recent data indicate that at room temperature the cell degradation in a longer t wait is worse than in a shorter t . wait 20) Therefore, the origin of the cell degradation during t wait between P/E cycles must be quantitatively clarified.…”

Section: Introductionmentioning

confidence: 99%

The origin of oxide degradation during time interval between program/erase cycles in NAND Flash memory devices

Chiu¹,

Tsai²,

Chang³

et al. 2021

Jpn. J. Appl. Phys.

Self Cite

View full text Add to dashboard Cite

show abstract

“…Reportedly, the time delay (t wait ) between P/E cycles is an important factor that affects the endurance characteristics [47][48][49][50][51]. Figure 14 shows that the ∆G m,max statistics become larger as t wait increases when the endurance test is performed at T R ; however, when T cyc increases to 85 °C, the trend is completely the opposite due to recovery from oxide damage through thermal excitation.…”

Section: Effect Of the Time Delay Between P/e Cyclesmentioning

confidence: 99%

“…Q CT obtained by fitting experimental data using Equation (8) for different values of t wait under T cyc of (a) 55 °C and (b) 85 °C. Reprinted from[47].…”

mentioning

confidence: 99%

Technique for Profiling the Cycling-Induced Oxide Trapped Charge in NAND Flash Memories

Chiu

Shirota

2021

Electronics

Self Cite

View full text Add to dashboard Cite

NAND Flash memories have gained tremendous attention owing to the increasing demand for storage capacity. This implies that NAND cells need to scale continuously to maintain the pace of technological evolution. Even though NAND Flash memory technology has evolved from a traditional 2D concept toward a 3D structure, the traditional reliability problems related to the tunnel oxide continue to persist. In this paper, we review several recent techniques for separating the effects of the oxide charge and tunneling current flow on the endurance characteristics, particularly the transconductance reduction (ΔGm,max) statistics. A detailed analysis allows us to obtain a model based on physical measurements that captures the main features of various endurance testing procedures. The investigated phenomena and results could be useful for the development of both conventional and emerging NAND Flash memories.

show abstract

“…Due to the structural characteristics of using common source line, the program/erase cycle increases in proportion to the increasing block size in the 3D NAND that performs the erase operation in units of blocks. When the program/erase cycle is increased, the reliability of the device decreases due to various problems, such as the deterioration of the retention characteristics caused by the heat that is generated during the P/E operation, cell disturbance caused by the P/E operation, and the deterioration of the durability of the blocking oxide [11][12][13][14][15][16][17]. This problem can be improved by using a dummy WL to split the blocks and to erase only the selected blocks [18][19][20][21].…”

Section: Introductionmentioning

confidence: 99%

Optimal Bias Condition of Dummy WL for Sub-Block GIDL Erase Operation in 3D NAND Flash Memory

Kim

Kang

2022

Electronics

View full text Add to dashboard Cite

In this study, we have analyzed the optimal bias condition of dummy WL for the sub-block gate induced drain leakage (GIDL) erase operation in 16-layer 3D NAND flash memory. Three-dimensional NAND flash memory performs an erase operation in units of pages. Increasing the number of stacks increases the number of cells that are erased at one time, which can lead to undesirable durability degradation. In this case, the sub-block erase operation can reduce the burden on the cell by up to half, due to the erase operation. The distribution of the hole density (hDensity) and the potential, according to VDummy, was analyzed when block1 and block2 were erased by setting WL0:WL7 to block1, WL9:WL15 to block2, and WL8 to dummy WL. For the simulation results, block1 showed an optimal distribution of hDensity and potential in the order of 20 V, floating, and 0 V. In block2, the optimal distribution of hDensity was shown in the order of 20 V, floating, and 0 V, with the optimal distribution of the potential in the order of floating and 0 V.

show abstract

Impact of Program/Erase Cycling Interval on the Transconductance Distribution of NAND Flash Memory Devices

Cited by 7 publications

References 27 publications

The origin of oxide degradation during time interval between program/erase cycles in NAND Flash memory devices

The origin of oxide degradation during time interval between program/erase cycles in NAND Flash memory devices

Technique for Profiling the Cycling-Induced Oxide Trapped Charge in NAND Flash Memories

Optimal Bias Condition of Dummy WL for Sub-Block GIDL Erase Operation in 3D NAND Flash Memory

Contact Info

Product

Resources

About