Impact of quasi-ballistic phonon transport on thermal properties in nanoscale devices: A Monte Carlo approach

Kukita, Kentaro; Adisusilo, Indra Nur; Kamakura, Yoshinari

doi:10.1109/iedm.2012.6479061

Cited by 9 publications

(5 citation statements)

References 15 publications

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“…9(a) shows a calculated contour plot of lattice temperature for a 6 nm BOX SOI MOSFET under operation using a device simulator [6], [30]. The maximum temperature point (hot spot) is located in the drain region, which is in agreement with the previous computational studies on deeply scaled devices [31], [32]. Thus, thermal characterization using average temperature in the gate electrode may lead to an underestimation of the SHE.…”

Section: A Temperature Distribution Within a Devicementioning

confidence: 65%

Direct Evaluation of Self-Heating Effects in Bulk and Ultra-Thin BOX SOI MOSFETs Using Four-Terminal Gate Resistance Technique

Takahashi

Matsuki

Shinada

et al. 2016

IEEE J. Electron Devices Soc.

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We demonstrate clear self-heating effects (SHE) of bulk and SOI MOSFETs for various SOI/BOX thicknesses including ultra-thin 6 nm BOX, which was not detected by the AC conductance method, using the four-terminal gate resistance technique. We clarify that the SHE in bulk MOSFETs originates from the degradation of thermal conductivity in a heavily doped well region. The strong chip-temperature dependence of the SHE was observed only in bulk MOSFETs. As results of the chip temperature-dependent SHE of bulk devices and the SHE suppression by BOX thinning, the device temperature of ultrathin BOX SOI MOSFETs is close to that of bulk MOSFETs at an elevated chip temperature, which suggests the thermal advantage of extremely thin BOX structures.

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Section: A Temperature Distribution Within a Devicementioning

confidence: 65%

Direct Evaluation of Self-Heating Effects in Bulk and Ultra-Thin BOX SOI MOSFETs Using Four-Terminal Gate Resistance Technique

Takahashi

Matsuki

Shinada

et al. 2016

IEEE J. Electron Devices Soc.

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“…Furthermore, phonon ballistic transport is also expected to have an effect 56,57 for small dimensions, which means that correct information about not only about j but also hvi and hki is important. We thus believe that the MC simulation approach presented in this work can be a useful tool for accurately assessing the heat conduction properties of nanoscale devices.…”

Section: Discussionmentioning

confidence: 99%

Monte Carlo simulation of phonon transport in silicon including a realistic dispersion relation

Kukita

Kamakura

2013

Journal of Applied Physics

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Thermal conductivities in bulk Si and Si films are analyzed using a Monte Carlo method to solve the phonon Boltzmann transport equation. By taking into account the realistic phonon dispersion relation calculated from the adiabatic bond charge model along with pure diffuse boundary scattering based on Lambert's law, simulated results that were in good agreement with the experimental ones were obtained. In addition, it was found that the approximated dispersion curves fitted along the [100] direction underestimate the density of states for mobile phonons, which results in a smaller specific heat and a longer phonon mean free path. The resulting impact on the simulation of heat transfer in nanostructures is discussed. V C 2013 AIP Publishing LLC.

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“…The small region of the high electric field near the drain gives rise to a strongly localized hot spot. The hot spot is only in the range of tens of nanometers and has a higher temperature than those predicated by the classic diffusion theory [21,22]. The extracted temperature and the measured current I ds under the saturation condition (V gs = V ds = 1.5 for the n-channel, V gs = V ds = −1.5 for the p-channel) dependence on the gate length are shown in figure 8.…”

Section: Thermal Resistancementioning

confidence: 95%

Experimental investigation of self heating effect (SHE) in multiple-fin SOI FinFETs

Jiang

Chen

et al. 2014

Semicond. Sci. Technol.

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In this work, the self-heating effect (SHE) on metal gate multiple-fin SOI FinFETs is studied by adopting the ac conductance technique to extract the thermal resistance and temperature rise in both n-channel and p-channel SOI FinFETs with various geometry parameters. It is shown that the SHE degrades by over 10% of the saturation output current in the n-channel and by over 7% in the p-channel. The extracted thermal resistances R th increase with the scaled down gate length, reducing the number of fin and shrinking the fin width. The temperature rise caused by the SHE increases with the scaled down gate length, increasing the number of fin and shrinking the fin width under the saturated operation condition. Additionally, due to a larger power density in the n-channel SOI FinFETs under the same bias condition, the temperature in the n-channel FinFETs is higher than that in the p-channel FinFETs. Because the Si thermal conductivity decreases as the temperature increases, R th is larger in the n-channel FinFETs than in the p-channel FinFETs. Therefore, tradeoffs have to be made between the thermal properties and the device's electrical performance by careful design optimizations of SOI FinFETs.

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Impact of quasi-ballistic phonon transport on thermal properties in nanoscale devices: A Monte Carlo approach

Cited by 9 publications

References 15 publications

Direct Evaluation of Self-Heating Effects in Bulk and Ultra-Thin BOX SOI MOSFETs Using Four-Terminal Gate Resistance Technique

Direct Evaluation of Self-Heating Effects in Bulk and Ultra-Thin BOX SOI MOSFETs Using Four-Terminal Gate Resistance Technique

Monte Carlo simulation of phonon transport in silicon including a realistic dispersion relation

Experimental investigation of self heating effect (SHE) in multiple-fin SOI FinFETs

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