Impact of resistance drift on multilevel PCM design

Chiu, Yi-Hsuan; Liao, Yunlong; Chiang, Meng-Hsueh; Lin, Chia-Long; Hsu, Wei‐Chou; Chiang, Pei-Chia; Hsu, Yu‐I; Liu, Wen-Hsing; Sheu, Shyh-Shyuan; Su, Keng-Li; Kao, Ming-Jer; Tsai, Ming-Jinn

doi:10.1109/icicdt.2010.5510298

Cited by 4 publications

(2 citation statements)

References 5 publications

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“…This phenomenon is known as resistance drift. Resistance drift is believed to be the result of structural relaxation (SR) physical phenomena, which is a thermally-activated, atomic rearrangement of the amorphous structure [11]. It has been observed [9,12] that drift is much more significant on high resistance states (e.g.…”

Section: B Resistance Drift and Its Impact On Mlcmentioning

confidence: 99%

Helmet: A resistance drift resilient architecture for multi-level cell phase change memory system

Zhang

2011

2011 IEEE/IFIP 41st International Conference on Dependable Systems &Amp; Networks (DSN)

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Phase change memory (PCM) is emerging as a promising solution for future memory systems and disk caches. As a type of resistive memory, PCM relies on the electrical resistance of Ge 2 Sb 2 Te 5 (GST) to represent stored information. With the adoption of multi-level programming PCM devices, unwanted resistance drift is becoming an increasing reliability concern in future high-density, multi-level cell PCM systems. To address this issue without incurring a significant storage and performance overhead in ECC, conventional design employs a conservative approach, which increases the resistance margin between two adjacent states to combat resistance drift. In this paper, we show that the wider margin adversely impacts the lowpower benefit of PCM by incurring up to 2.3X power overhead and causes up to 100X lifetime reduction, thereby exacerbating the wear-out issue. To tolerate resistance drift, we proposed Helmet, a multi-level cell phase change memory architecture that can cost-effectively reduce the readout error rate due to drift. Therefore, we can relax the requirement on margin size, while preserving the readout reliability of the conservative approach, and consequently minimize the power and endurance overhead due to drift. Simulation results show that our techniques are able to decrease the error rate by an average of 87%. Alternatively, for satisfying the same reliability target, our schemes can achieve 28% power savings and a 15X endurance enhancement due to the reduced margin size when compared to the conservative approach.

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Section: B Resistance Drift and Its Impact On Mlcmentioning

confidence: 99%

Helmet: A resistance drift resilient architecture for multi-level cell phase change memory system

Zhang

2011

2011 IEEE/IFIP 41st International Conference on Dependable Systems &Amp; Networks (DSN)

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“…Without loss of generality, we demonstrate the design-technology tradeoff for an OxRRAM-based neuromorphic PE, where each NVM cell can be programmed to the following four resistance levels (i.e., 2-bit per synapse) -1.5 KΩ, 5.78 KΩ, 13.6 KΩ, and 73 KΩ [19,20,31,64,74]. Furthermore, we show our analysis for four process technology nodes -16nm, 22nm, 32nm, and 45nm, which are obtained from our technology provider.…”

Section: Design-technology Tradeoff Analysismentioning

confidence: 99%

Design-Technology Co-Optimization for NVM-based Neuromorphic Processing Elements

Song¹,

Balaji²,

Das³

et al. 2022

Preprint

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An emerging use-case of machine learning (ML) is to train a model on a high-performance system and deploy the trained model on energy-constrained embedded systems. Neuromorphic hardware platforms, which operate on principles of the biological brain, can significantly lower the energy overhead of a machine learning inference task, making these platforms an attractive solution for embedded ML systems. We present a designtechnology tradeoff analysis to implement such inference tasks on the processing elements (PEs) of a Non-Volatile Memory (NVM)-based neuromorphic hardware. Through detailed circuit-level simulations at scaled process technology nodes, we show the negative impact of technology scaling on the information-processing latency, which impacts the quality-of-service (QoS) of an embedded ML system. At a finer granularity, the latency inside a PE depends on 1) the delay introduced by parasitic components on its current paths, and 2) the varying delay to sense different resistance states of its NVM cells. Based on these two observations, we make the following three contributions. First, on the technology front, we propose an optimization scheme where the NVM resistance state that takes the longest time to sense is set on current paths having the least delay, and vice versa, reducing the average PE latency, which improves the QoS. Second, on the architecture front, we introduce isolation transistors within each PE to partition it into regions that can be individually power-gated, reducing both latency and energy. Finally, on the system-software front, we propose a mechanism to leverage the proposed technological and architectural enhancements when implementing a machine-learning inference task on neuromorphic PEs of the hardware. Evaluations with a recent neuromorphic hardware architecture show that our proposed design-technology co-optimization approach improves both performance and energy efficiency of machine-learning inference tasks without incurring high cost-per-bit. CCS Concepts: • Hardware → Neural systems; Emerging languages and compilers; Emerging tools and methodologies; • Computer systems organization → Data flow architectures; Neural networks.

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Design-Technology Co-Optimization for NVM-Based Neuromorphic Processing Elements

Song

Balaji

Das

et al. 2022

ACM Trans. Embed. Comput. Syst.

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An emerging use-case of machine learning (ML) is to train a model on a high-performance system and deploy the trained model on energy-constrained embedded systems. Neuromorphic hardware platforms, which operate on principles of the biological brain, can significantly lower the energy overhead of a machine learning inference task, making these platforms an attractive solution for embedded ML systems. We present a design-technology tradeoff analysis to implement such inference tasks on the processing elements (PEs) of a Non-Volatile Memory (NVM)-based neuromorphic hardware. Through detailed circuit-level simulations at scaled process technology nodes, we show the negative impact of technology scaling on the information-processing latency, which impacts the quality-of-service (QoS) of an embedded ML system. At a finer granularity, the latency inside a PE depends on 1) the delay introduced by parasitic components on its current paths, and 2) the varying delay to sense different resistance states of its NVM cells. Based on these two observations, we make the following three contributions. First, on the technology front, we propose an optimization scheme where the NVM resistance state that takes the longest time to sense is set on current paths having the least delay, and vice versa, reducing the average PE latency, which improves the QoS. Second, on the architecture front, we introduce isolation transistors within each PE to partition it into regions that can be individually power-gated, reducing both latency and energy. Finally, on the system-software front, we propose a mechanism to leverage the proposed technological and architectural enhancements when implementing a machine-learning inference task on neuromorphic PEs of the hardware. Evaluations with a recent neuromorphic hardware architecture show that our proposed design-technology co-optimization approach improves both performance and energy efficiency of machine-learning inference tasks without incurring high cost-per-bit.

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Impact of resistance drift on multilevel PCM design

Cited by 4 publications

References 5 publications

Helmet: A resistance drift resilient architecture for multi-level cell phase change memory system

Helmet: A resistance drift resilient architecture for multi-level cell phase change memory system

Design-Technology Co-Optimization for NVM-based Neuromorphic Processing Elements

Design-Technology Co-Optimization for NVM-Based Neuromorphic Processing Elements

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