Impact of Scaling on Analog Performance and Associated Modeling Needs

Linearity and mobility degradation in strained Si MOSFETs with thin gate dielectrics

“…Although the measurements here indicate that mobility degradation is independent of strain, more advanced MOSFET models than (1) and more advanced mobility models than (2) would be needed to understand the impact of strain/germanium-related surface morphological properties on the high field mobility in strained Si layers. This is due to the increase in the electron affinity with tensile strain.…”

“…The miniaturization of the metal oxide on semiconductor field effect transistor (MOSFET) has made complimentary metal oxide on semiconductor (CMOS) devices considerable radio frequency (RF) contenders where bipolars and high-electronmobility-transistors are traditionally dominant [1,2]. Strain engineering in deep submicrometer CMOS devices has further improved the high speed performance required for RF implementation [3].…”

“…However in analog/mixed-signal applications, other metrics like noise and linearity are important [4][5][6]. Linearity is particularly of interest in CMOS devices since MOSFETs exhibit better linearity than bipolars [2]. In a perfectly linear MOSFET, a signal with a single harmonic at the input would yield an output signal at the same frequency.…”

“…Another indicator of linearity is the V IP3 which is defined as the extrapolated gate voltage (V GS ) bias at which the amplitudes of the 1 st and 3 rd order derivatives of I DS are equal [2,[7][8][9][10][11]. The V IP3 can be measured from MOSFET DC I DS vs. V GS characteristics and is given by …”

“…Gate dielectric scaling and higher substrate doping has increased the transverse electric fields and hence, mobility degradation from surface roughness scattering. A 2 nd order mobility degradation model was developed to account for mobility reduction related to (V GS -V TH ) 2 at high vertical fields where V TH is the threshold voltage [12]. The effective mobility, µ EFF can be expressed as…”