Impact of Sidewall Roughness on Integrated Bragg Gratings

Lithography simulation for the fabrication of silicon photonic devices with deep-ultraviolet lithography

“…The measured extinction ratio is less than that predicted by the FDTD simulation, which is common for integrated Bragg gratings [2]. This discrepancy may arise from a number of factors, including sidewall roughness [7], fabrication nonuniformity [6], random defects, etc. designed with 20 nm square corrugations.…”

Coupler-apodized Bragg-grating add–drop filter

“…However, the experimental results are still worse than the simulation, where the sidelobes are far below −40 dB. We attribute this performance deterioration to phase noise induced by the sidewall roughness and wafer nonuniformity [10].…”

“…Their waveguide perturbations are typically in the range of 10 to 100 nm, comparable to or even smaller than the lithography wavelength (typically 193 or 248 nm) used for mass production. Therefore, it is challenging to accurately control grating profiles for efficient apodization due to the lithography smoothing effects [9] and fabrication-caused phase errors [10]. A sidelobe suppression ratio of 10 to 15 dB is among the best demonstrated results on submicrometer silicon waveguides fabricated using deep-UV lithography [11].…”

Dual phase-shift Bragg grating silicon photonic modulator operating up to 60 Gb/s

“…Without terminations, the power consumption would come mainly from the PN junction capacitance [16] leading to power consumption similar to the one reported in [20]. The bias voltage could also be lowered by reducing the mismatch between the two resonant cavities through the use of Bragg grating phase noise reduction techniques [25,26]. More efficient phase-shifters based on an interleaved PN junction [27], a SISCAP junction [28] or vertical junctions [29] could also help achieving lower driving voltages and lower bias voltages.…”