Impact of SiO&lt;inf&gt;2&lt;/inf&gt;/Si interface micro-roughness on SILC distribution and dielectric breakdown: A comparative study with atomically flattened devices

Park, Hyeonwoo; Goto, Tetsuya; Kuroda, Rihito; Teramoto, Akinobu; Suwa, Tomoyuki; Kimoto, Daiki; Sugawa, Shigetoshi

doi:10.1109/irps.2017.7936364

Cited by 8 publications

(5 citation statements)

References 21 publications

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“…12]. The electric field is enhanced with increasing Rmax and decreasing , being consistent with similar calculations performed on SiO2/Si in a much more restricted range of Rmax, microroughness values, typically less than 1.5 nm [9]. Figure 12 clearly puts in evidence the relatively low impact of  regarding the major impact of Rmax within the 1 nm to 85 nm roughness range.…”

Section: Electrical Resultssupporting

confidence: 82%

Impact of roughness of TiN bottom electrode on the forming voltage of HfO2 based resistive memories

Charpin‐Nicolle

Bonvalot

Sommer

et al. 2020

Microelectronic Engineering

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In this work, we study the impact of roughness of TiN bottom electrode on the forming voltage of 1R TiN/HfO2/Ti/TiN based ReRAM devices. A novel and atypical strategy is proposed to induce a controlled roughness of the bottom electrode, using various plasma chemistries. The forming voltage is observed to be directly linked to the roughness of the bottom electrode, over a large range of roughness values. TCAD simulation studies enable an estimate of the electrical field in the oxide inducing the forming step and confirm the dominant impact of roughness on the switching properties of ReRAM devices.

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Section: Electrical Resultssupporting

confidence: 82%

Impact of roughness of TiN bottom electrode on the forming voltage of HfO2 based resistive memories

Charpin‐Nicolle

Bonvalot

Sommer

et al. 2020

Microelectronic Engineering

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“…As for the SiO 2 film, some previous researches have reported that interface roughness greatly impacts their leakage currents because the electric field is easily concentrated in a local area. 34) Therefore, it can also be assumed that the increase of the electric field concentration by the rough MgO film results in a large current in the same MIM area. In this study, we did not apply thermal annealing to the MIM samples in order to investigate the influence of the MgO roughness only.…”

Section: Resultsmentioning

confidence: 99%

Impact of CoFeB surface roughness on reliability of MgO films in CoFeB/MgO/CoFeB magnetic tunnel junction

Park¹,

Teramoto

Tsuchimoto

et al. 2019

Jpn. J. Appl. Phys.

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We investigated the impact of the interface roughness in W-CoFeB-MgO-CoFeB-W structures on MgO reliability using the atomic force microscopy images of a MgO underlayer surface and I-V measurements. As a result, the electric current in the MgO film increased as the MgO underlayer surface roughness increased. We assumed that this phenomenon is caused by the local electric field concentration, and verified it by comparing the two electric field concentration values simulated from the AFM images and calculated from the I-V measurements. These two electric field concentrations calculated from the different results have a strong correlation to each other. It is concluded that the current of the MgO film is increased by the large roughness between MgO and the electrodes. This causes the large current variation in memory cells in magnetic random access memory (MRAM), then it leads to a small margin in memory operation.

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“…In dielectric breakdown characteristics, the definition of defect density per unit gate area using the Poisson distribution was reported. [28][29][30] Likewise, the density defects that generate a certain SILC can be defined using the following equation: 31)…”

Section: Resultsmentioning

confidence: 99%

Experimental investigation of localized stress-induced leakage current distribution in gate dielectrics using array test circuit

Park

Teramoto

Kuroda

et al. 2018

Jpn. J. Appl. Phys.

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Localized stress-induced leakage current (SILC) has become a major problem in the reliability of flash memories. To reduce it, clarifying the SILC mechanism is important, and statistical measurement and analysis have to be carried out. In this study, we applied an array test circuit that can measure the SILC distribution of more than 80,000 nMOSFETs with various gate areas at a high speed (within 80 s) and a high accuracy (on the 10 %17 A current order). The results clarified that the distributions of localized SILC in different gate areas follow a universal distribution assuming the same SILC defect density distribution per unit area, and the current of localized SILC defects does not scale down with the gate area. Moreover, the distribution of SILC defect density and its dependence on the oxide field for measurement (E OX-Measure ) were experimentally determined for fabricated devices.

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Impact of SiO<inf>2</inf>/Si interface micro-roughness on SILC distribution and dielectric breakdown: A comparative study with atomically flattened devices

Cited by 8 publications

References 21 publications

Impact of roughness of TiN bottom electrode on the forming voltage of HfO2 based resistive memories

Impact of roughness of TiN bottom electrode on the forming voltage of HfO2 based resistive memories

Impact of CoFeB surface roughness on reliability of MgO films in CoFeB/MgO/CoFeB magnetic tunnel junction

Experimental investigation of localized stress-induced leakage current distribution in gate dielectrics using array test circuit

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