Impact of stress effect on triple material gate step-FinFET with DC and AC analysis

Das, Rinku Rani; Chowdhury, Arijit; Chakraborty, Apurba; Maity, Santanu

doi:10.1007/s00542-019-04727-2

Cited by 10 publications

(6 citation statements)

References 25 publications

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“…Various updated MOS structures have been suggested to enhance efficiency, including dual gate (DG), surrounding gate (SG), and independent-gate (IG) MOSFET designs. [3].…”

Section: Introductionmentioning

confidence: 99%

“…The scaling of Fin width helps to recover the degradation of short channel parameters due to high-k integration. Das et al [5] proposed a triple material gate (TMG) step FinFET to analyze the stress effect on device performance. In TMG FinFET, the surface potential is higher than the conventional FinFET, which reduces the electric field effect at the drain end and enhances the driving current.…”

Section: Introductionmentioning

confidence: 99%

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Multi-Channel Step FinFET With Spacer Engineering

Das,

James

2024

IEEE Access

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Multi-channel FinFET (M ch -FinFET) is an emerging device having promising use due to its excellent driving capability. In this paper, we have investigated the significance of multiple channels of FinFET configuration. We have examined the performance of the multi-channel-based step FinFET (M chstep FinFET) structure with spacer engineering. The results obtained from this simulation work indicate that M ch -step FinFET is a good competitor for future improvisation of CMOS technology. The proposed device has improved drain conductivity, transconductance (G m ), intrinsic gain (A v ), and drain conductance (G d ) performance by introducing high-K dielectric spacer material by 38.2%,46.12%, 88.57%, and 22.55%, respectively. The proposed device with a spacer is preferable to obtain better performance regarding ON current and device efficiency.INDEX TERMS Semiconductor device, Short Channel effect (SCE), Subthreshold swing (SS), Bipolar Junction transistor (BJT).

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“…Various updated MOS structures have been suggested to enhance efficiency, including dual gate (DG), surrounding gate (SG), and independent-gate (IG) MOSFET designs. [3].…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Multi-Channel Step FinFET With Spacer Engineering

Das,

James

2024

IEEE Access

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“…Aggressive downscaling of device parameters limits the performance of these all planar MOS structures [12] to meet the requirements of the International Technology Roadmap for Semiconductor Projection (ITRS) [13] and device faced a serious unwanted problem called short channel effects (SCEs). Drain-induced barrier lowering (DIBL), sub-threshold swing (SS), threshold voltage variation, and mobility degradation are the various SCEs [14][15] .…”

Section: Introductionmentioning

confidence: 99%

Effect of positive and negative interface trap charges on the performance of M-FinFET and its RF/linearity analysis

Das

Chowdhury

Chakroborty

et al. 2021

Preprint

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Multiple Fins structured FinFET (M-FinFET) is a promising semiconductor device for future improvisation of CMOS technology. In this paper, we investigate the impact of interface trap charges (positive and negative trap) at the HfO2/Si interface in M-FinFET for the first time. The various important DC attributes, RF/analog, and linearity metrics are studied in presence and absence of traps. Simultaneously, the various trap concentration effect on the characteristics of M-FinFET are also observed. The results show that the introduction of interface trap charges (ITC) has optimized the ON current, OFF current, and also improves sub-threshold swing (SS) characteristics as compared to no trap condition. It is observed that positive trap having trap concentration of 1012/cm2 enhances the ION ~5.14x, SS by 44.75%, and various important RF/analog parameter such as transconductance (Gm) improves by a factor 5, device efficiency by 7.4% and intrinsic gain (Av) 80.4%. On the other hand, linearity parameters like VIP2, VIP3 and 1 dB compression point show better performance in presence of positive and negative trap.

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“…Nowadays, researchers have developed various modified FinFET architecture while following the ITRS roadmap and Moore's law 10 . DMG (double material gate) FinFET, 11 TMG (triple material gate) FinFET, Step FinFET, 12 GAA (gate‐all‐around) 13 FinFET, cylindrical FinFET, omega gate FinFET, and multi Fin FinFET are the various inventive configuration of FinFET structure 14 . Vinay et al 15 compared the performance of nanowire FET and bulk‐Si FinFET device for the 5 nm technology node.…”

Section: Introductionmentioning

confidence: 99%

Impact of temperature on radio frequency/linearity and harmonic distortion characteristics of Ge multi‐channel fin shaped field‐effect transistor

Das

Maity

Chowdhury

et al. 2021

Int J RF Mic Comp-Aid Eng

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This dissertation demonstrates the reliability issues associated with the temperature of Ge multi‐channel fin shaped field‐effect transistor (Mch‐FinFET). Temperature dependence on short channel effectss such as threshold voltage (Vth), sub‐threshold swing (SS), and switching ratio are observed. The variation in temperature on various important radio frequency (RE)/analog, linearity, and harmonic distortion characteristics are studied and analyzed over a wide range of temperatures (300–500 K). The simulation study revealed that Mch‐FinFET devices exhibit 61.6% improvement in ION with minimum SS value. The improvement of SS, switching ratio and Vth can be observed with temperature fall. The enhancement in performance of various RF/analog attributes such transconductance, device efficiency, transconductance frequency product, gain frequency product, cut‐off frequency, and intrinsic gain with lowering of temperature. However, Mch‐FinFET device provides a significant improvement of higher‐order current and voltage intercept points such as IIP3, VIP2, VIP3, and 1 dB compression point with lesser harmonic distortion such as HD2, HD3, and THD at elevated temperature. The superior efficiency of DC and RF/analog attributes, greater linearity, and minor harmonic distortion performance of Mch‐FinFET make it more considerable to design low power Complementary metal–oxide–semiconductor (CMOS) circuits.

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Impact of stress effect on triple material gate step-FinFET with DC and AC analysis

Cited by 10 publications

References 25 publications

Multi-Channel Step FinFET With Spacer Engineering

Multi-Channel Step FinFET With Spacer Engineering

Effect of positive and negative interface trap charges on the performance of M-FinFET and its RF/linearity analysis

Impact of temperature on radio frequency/linearity and harmonic distortion characteristics of Ge multi‐channel fin shaped field‐effect transistor

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