Impact of structural process variation on junctionless silicon nanotube FET

Ambika, R.; Srinivasan, R.

doi:10.1088/2043-6254/aadc33

Cited by 5 publications

(2 citation statements)

References 18 publications

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“…This clearly indicates that the junctionless device is significantly related to process and geometrical parameters as it shrinks into nano scale regime. The study of structural and geometrical variability on the performance jumctionless transistors have also been conducted recently by khorramrouz et al (2018) and Ambika and Srinivasan et al (2018) [19,20]. Based on their observation, the structural and geometrical parameters such as thickness of silicon, thickness of insulator, channel length and etc.…”

Section: Introductionmentioning

confidence: 99%

Performance analysis of ultrathin junctionless double gate vertical MOSFETs

Kaharudin¹,

Napiah²,

Salehuddin³

et al. 2019

Bulletin EEI

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The main challenge in MOSFET minituarization is to form an ultra-shallow source/drain (S/D) junction with high doping concentration gradient, which requires an intricate S/D and channel engineering. Junctionless MOSFET configuration is an alternative solution for this issue as the junction and doping gradients is totally eliminated. A process simulation has been developed to investigate the impact of junctionless configuration on the double-gate vertical MOSFET. The result proves that the performance of junctionless double-gate vertical MOSFETs (JLDGVM) are superior to the conventional junctioned double-gate vertical MOSFETs (JDGVM). The results reveal that the drain current (ID) of the n-JLVDGM and p-JLVDGM could be tremendously enhanced by 57% and 60% respectively as the junctionless configuration was applied to the double-gate vertical MOSFET. In addition, junctionless devices also exhibit larger ION/IOFF ratio and smaller subthreshold slope compared to the junction devices, implying that the junctionless devices have better power consumption and faster switching capability.

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Section: Introductionmentioning

confidence: 99%

Performance analysis of ultrathin junctionless double gate vertical MOSFETs

Kaharudin¹,

Napiah²,

Salehuddin³

et al. 2019

Bulletin EEI

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“…4 Recently Carbon Nanotube Field Effect Transistor (CNTFET) have been fabricated successfully. 5 From the fabrication that have been done, CNTFET shown a better performance than conventional MOSFET with the same size. Important electrical and mechanical characteristic of carbon nanotube is shown in Table I.…”

mentioning

confidence: 99%

Characterizing the Carbon Nanotube Field Effect Transistor: A Geometric Variation Study

Suhaimi

Hussin

2020

ECS J. Solid State Sci. Technol.

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This research is focusing on the geometrical variation effects of carbon nanotube field effect transistor (CNTFET). The characteristics of the CNTFET are observed based on different CNTFET diameter, the oxide thickness and the chiral vector. The characteristics under study includes the drain current, ION/IOFF, the quantum capacitance as well as the threshold voltage. The work is carried out using CNTFET labtool of nanoHUB.org includes the FETToy Simulator which based MATLAB script that calculate the ballistic I-V characteristic and MSL Nanomaterials Simulator that used to design and analyse electronic properties of various nano materials. The results show that small difference of chiral vector, (4, 0) will produce large threshold voltage. The quantum capacitance is observed to be decreased with decreasing oxide thickness as gate voltage reaches 0.5 V and above. The ION/IOFF ratio will increase as the CNTFET diameter increased. As a conclusion, CNTFET is a perfect choice to substitute conventional MOSFET with their remarkable features.

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