Impact of the drain and source extensions on nanoscale Double-Gate Junctionless MOSFET analog and RF performances

Bentrcia, Toufik; Djeffal, F.; Chebaki, Elasaad; Arar, D.

doi:10.1016/j.mssp.2015.07.060

Cited by 17 publications

(13 citation statements)

References 9 publications

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“…The increase in C gs and C gd increases the C gg due to which the K value rises. The same can be inferred from Equation 9, where K dependency on f T , g m , C gs , and C gd is given by Sivasankaran and Mallick. 18 k≅…”

Section: Rf Performance Of Dgjltmentioning

confidence: 79%

“…The JLT has received attention for analog/radio frequency (RF) applications due to its improved intrinsic gain and maximum oscillation frequency ( f max ) . Many works were carried on JLTs about enhancing the electrostatic integrity using a high k spacer, drain/source extension, and gate work function on analog and RF applications . Impact of process parameter variation on the analog and RF performance of the multigate is studied .…”

Section: Introductionmentioning

confidence: 99%

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Impact of high k spacer on RF stability performance of double gate junctionless transistor

Raju

Sivasankaran

2018

Int J Numerical Modelling

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In this paper, radio frequency (RF) stability performance of double gate junctionless transistor for different spacer material, the width of spacer, and bias conditions is reported. The impact of gate oxide thickness and gate work function on RF performance of double gate junctionless transistor is also presented. The analog and RF figure of merit, namely, intrinsic gain, unity gain cut-off frequency, stern's stability factor, critical frequency, maximum attainable gain, and maximum stable gain, are investigated with the help of numerical simulation. The result shows that the fringing fields of high k spacers have a major impact on the gate to source and gate to drain capacitance. The device design guideline along with bias and geometrical parameters are reported for the optimized structure. The optimized device structure exhibits better RF stability. KEYWORDS double gate junctionless transistor (DGJLT), high k spacer, MAG, MSG, RF stability, unity gain cutoff frequency 1 | INTRODUCTIONAccording to the International Technology Roadmap for Semiconductors, alternative metal-oxide-semiconductor field-effect transistor (MOSFET) structures serve the need for devices beyond 16 nm. 1 One of the promising devices which can substitute the conventional MOSFET is junctionless transistor (JLT). 2 Junctionless transistor does not have PN junctions because source, channel, and drain are of same doping, which overcomes the problems associated with doping profile of MOSFETs. It also offers many advantages over conventional bulk MOSFETs such as better scalability, reduced short channel effects, simple fabrication process flow, and low thermal budgets after gate formation. [3][4][5] The JLT has received attention for analog/radio frequency (RF) applications due to its improved intrinsic gain and maximum oscillation frequency ( f max ). 6 Many works were carried on JLTs about enhancing the electrostatic integrity using a high k spacer, drain/source extension, and gate work function on analog and RF applications. 7-12 Impact of process parameter variation on the analog and RF performance of the multigate is studied. 13 The RF model was developed to extract the parameters like cut-off frequency ( f T ), input capacitance, and distribute channel resistance of junctionless silicon nanowire MOSFET. 14 The quantum mechanical model of gate all around nanowire MOSFET is developed to examine the effect of high k gate dielectric on the electrostatics and device performance. 15 The reliability issues of graded channel junctionless multigate transistor in analog performance are investigated. 16 From the literature review, we found that many studies were carried on analog and RF performance of JLTs. However, RF stability study on JLTs is not reported, which is an important figure of merit for the design of RF amplifiers or

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Section: Rf Performance Of Dgjltmentioning

confidence: 79%

Section: Introductionmentioning

confidence: 99%

Impact of high k spacer on RF stability performance of double gate junctionless transistor

Raju

Sivasankaran

2018

Int J Numerical Modelling

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“…The cut-off frequency is a relevant RF performance measure since it represents the frequency for which the current gain of the device is unity [24]. The transconductance and the cut-off frequency expressions are given by the following formula [25]…”

Section: Surrogate Metamodellingmentioning

confidence: 99%

Approach for designing and modelling of nanoscale DG MOSFET devices using Kriging metamodelling technique

Bentrcia

Djeffal

Chebaki

2017

IET Circuits, Devices & Syst

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In this study, the authors focus mainly on the investigation of Kriging interpolation method to elaborate surrogate models of the nanoscale double-gate metal oxide silicon field effect transistors (DG MOSFET) analogue/RF performance under critical operational conditions. The elaboration of such models is made possible through the generation of computer experiments using ATLAS-2D simulator, where the numerical simulations or experimental measurements, account for the accurate behaviour of the device including the ageing phenomena, short channel and quantum confinement effects. The validity of the obtained Kriging models is tested by comparing the predicted responses of the device with their numerical counterpart in terms of some statistical criteria namely the sum of relative errors, the mean percentage of absolute errors and the correlation coefficient. It is also shown that the obtained Kriging interpolation models are precise enough to be used as objective functions in the context of a genetic algorithm optimisation with the aim of improving the device analogue/RF performance in terms of transconductance and cutoff frequency parameters. Therefore, this study may provide more insights regarding the investigation of surrogate modelling tools in the field of deep nanoscale devices especially with the intractable mission of developing physical based models at this scale for nanoelectronic simulators.

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“…The double gate (DG) MOSFET, the simplest structure among the multiple gate MOSFETs, is of great importance [3,4,5]. In this paper, the subthreshold swing (SS) is investigated for sub-20 nm asymmetric DGMOSFETs, having different top and bottom gate structures.…”

Section: Introductionmentioning

confidence: 99%

The Impact of Tunneling on the Subthreshold Swing in Sub-20 nm Asymmetric Double Gate MOSFETs

Jung

Dimitrijev²

2016

IJECE

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<p>This paper analyzes the subthreshold swing in asymmetric double gate MOSFETs with sub-20 nm channel lengths. The analysis of the carrier transport in the subthreshold region of these nano scaled MOSFET includes tunneling as an important additional mechanism to the thermionic emission. It is found that the subthreshold swing is increasing due to tunneling current and that the performance of nano scaled MOSFETs is degraded. The degradation of the subthreshold swing due to tunneling is quantified using analytical potential distribution and Wentzel–Kramers–Brillouin (WKB) approximation in this paper. This analytical approach is verified by two dimensional simulation. It is shown that the degradation of subthreshold swing increases with both reduction of channel length and increase of channel thickness. We also show that the subthreshold swing is increasing in case of different top and bottom gate oxide thicknesses.</p>

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Impact of the drain and source extensions on nanoscale Double-Gate Junctionless MOSFET analog and RF performances

Cited by 17 publications

References 9 publications

Impact of high k spacer on RF stability performance of double gate junctionless transistor

Impact of high k spacer on RF stability performance of double gate junctionless transistor

Approach for designing and modelling of nanoscale DG MOSFET devices using Kriging metamodelling technique

The Impact of Tunneling on the Subthreshold Swing in Sub-20 nm Asymmetric Double Gate MOSFETs

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