Impact of Threshold Computation Methods in Hardware Wavelet Denoising Implementations for Neural Signal Processing

Carta, Nicola; Pani, Danilo; Raffo, Luigi

doi:10.1007/978-3-319-26129-4_5

Cited by 3 publications

(5 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Implementations of 1-D DWT for signal de-noising, feature extraction, and pattern recognition and compression can be found in [8,9,18,19]. The conventional convolution-based DWT requires massive computations and consumes much area and power, which could be overcome by using the lifting-based scheme for the DWT, which is introduced by Sweldens [20].…”

Section: Related Workmentioning

confidence: 99%

“…As an example, the discrete wavelet transform (DWT) [5][6][7][8][9], a linear signal-processing technique that transforms a signal from the time domain to the wavelet domain [10], employs various techniques for signal decomposing into an orthonormal time series with different frequency bands. The signal decomposition is performed using a pyramid algorithm (PA) [10,11] or a recursive pyramid transform (RPT) [12].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Comparative Performance of Discrete Wavelet Transform Implementations Using Multiplierless

Alzaq¹,

Üstündağ²

2018

Wavelet Theory and Its Applications

View full text Add to dashboard Cite

Using discrete wavelet transform (DWT) in high-speed signal-processing applications imposes a high degree of care to hardware resource availability, latency, and power consumption. In this chapter, the design aspects and performance of multiplierless DWT is analyzed. We presented the two key multiplierless approaches, namely the distributed arithmetic algorithm (DAA) and the residue number system (RNS). We aim to estimate the performance requirements and hardware resources for each approach, allowing for the selection of proper algorithm and implementation of multi-level DAA-and RNS-based DWT. The design has been implemented and synthesized in Xilinx Virtex 6 ML605, taking advantage of Virtex 6's embedded block RAMs (BRAMs).

show abstract

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Comparative Performance of Discrete Wavelet Transform Implementations Using Multiplierless

Alzaq¹,

Üstündağ²

2018

Wavelet Theory and Its Applications

View full text Add to dashboard Cite

show abstract

“…Discrete wavelet transform (DWT) [1][2][3][4][5] is a linear signal processing technique that transforms a time domain signal to "wavelet" domain [6]. DWT is usually implemented using the finite impulse response (FIR) filter bank structures [7].…”

Section: Introductionmentioning

confidence: 99%

An optimized two-level discrete wavelet implementation using residue number system

Alzaq

Ustundag

2018

EURASIP J. Adv. Signal Process.

View full text Add to dashboard Cite

Using discrete wavelet transform (DWT) in high-speed signal processing applications imposes a high degree of caution to hardware resource availability, latency and power consumption. In this paper, we investigated the design and implementation aspects of a multiplier-free two-level DWT by using residue number system (RNS). The proposed two-level takes the advantage of performing the multiplication operations using only the memory without involving special multiplier units, which preserves valuable resources for other critical tasks within the FPGA. The design was implemented and synthesized in ZYNQ ZC706 development kit, taking advantage of embedded block RAMs (BRAMs). The results of the overall experimentations showed that there is a considerable improve in the proposed two-level DWT design with regard to latency and peak signal-to-noise ratio (PSNR) precision value in the final output.

show abstract

“…Discrete wavelet transform (DWT) [1][2][3], a linear signal processing technique that transforms a signal from the time domain to the wavelet domain [4], employs different algorithms for decomposing a signal into an orthonormal time series with different frequency bands. The signal analysis can be performed using either the pyramid algorithm (PA) [4] or recursive pyramid transform (RPT) [5].…”

Section: Introductionmentioning

confidence: 99%

“…However, RPT decomposes the signal x[n] into two parts using high-and low-pass filters, which can be implemented using filter banks [6]. 1-D DWT has been implemented for signal denoising, feature extraction, and pattern recognition and compression in [2,3,7,8]. The conventional convolution-based DWT requires massive computations and consumes much area and power, which could be overcome by using the lifting-based scheme for the DWT that was introduced by Sweldens [9].…”

Section: Introductionmentioning

confidence: 99%

A comparative analysis of 1-level multiplier-free discrete wavelet transform implementations on FPGAs

Alzaq¹,

Üstündağ²

2018

Turk J Elec Eng & Comp Sci

View full text Add to dashboard Cite

In this article, we investigated the design and implementation aspects of multilevel discrete wavelet transform (DWT) by employing a finite impulse response filter on field programmable gate array platform. We presented two key multiplication-free architectures, namely, the distributed arithmetic algorithm (DAA) and residue number system (RNS). Our goal is to estimate the performance requirements and hardware resources for each approach, allowing for selection of the proper algorithm and implementation of multilevel DAA-and RNS-based DWT. The design has been implemented and synthesized in Xilinx Virtex 6 ML605, taking advantage of Virtex 6's embedded block RAMs. The results reveal that the DAA-based approach is appropriate for a small number of filter taps, while the RNS-based approach would be more appropriate for more than 10 filter taps, yet both DAA-and RNS-based approaches offer high signal quality with peak signal-to-noise ratio as 73.5 and 56.5 dB, respectively.

show abstract

Impact of Threshold Computation Methods in Hardware Wavelet Denoising Implementations for Neural Signal Processing

Cited by 3 publications

References 15 publications

A Comparative Performance of Discrete Wavelet Transform Implementations Using Multiplierless

A Comparative Performance of Discrete Wavelet Transform Implementations Using Multiplierless

An optimized two-level discrete wavelet implementation using residue number system

A comparative analysis of 1-level multiplier-free discrete wavelet transform implementations on FPGAs

Contact Info

Product

Resources

About