Objective: Hand amputation is a highly disabling event, which significantly affects quality of life. An effective hand replacement can be achieved if the user, in addition to motor functions, is provided with the sensations that are naturally perceived while grasping and moving. Intraneural peripheral electrodes have shown promising results toward the restoration of the sense of touch. However, the long-term usability and clinical relevance of intraneural sensory feedback have not yet been clearly demonstrated. Methods: To this aim, we performed a six months clinical study with three trans-radial amputees who received implants of transverse intrafascicular multichannel electrodes (TIMEs) in their median and ulnar nerves. After calibration, electrical stimulation was delivered through the TIMEs connected to artificial sensors in the digits of a prosthesis to generate sensory feedback, which was then used by the subjects while performing different grasping tasks. Results: All the subjects, notwithstanding their important clinical differences, reported stimulationinduced sensations from the phantom hand for the whole duration of the trial. They also successfully integrated the sensory feedback into their motor control strategies while performing experimental tests simulating tasks of real life (with and without the support of vision). Finally, they reported a decrement of their phantom limb pain and a general improvement in mood state. Interpretation: The promising results achieved with all subjects show the feasibility of the use of intraneural stimulation in clinical settings.

With increasing communication demands of processor and memory cores in Systems on Chips (SoCs), scalable Networks on Chips (NoCs) are needed to interconnect the cores. For the use of NoCs to be feasible in today's industrial designs, a custom-tailored, application-specific NoC that satisfies the design objectives and constraints of the targeted application domain is required. In this work, we present a design methodology that automates the synthesis of such application-specific NoC architectures. We present a floorplan aware design method that considers the wiring complexity of the NoC during the topology synthesis process. This leads to detecting timing violations on the NoC links early in the design cycle and to have accurate power estimations of the interconnect. We incorporate mechanisms to prevent deadlocks during routing, which is critical for proper operation of NoCs. We integrate the NoC synthesis method with an existing design flow, automating NoC synthesis, generation, simulation and physical design processes. We also present ways to ensure design convergence across the levels. Experiments on several SoC benchmarks are presented, which show that the synthesized topologies provide a large reduction in network power consumption (2.78× on average) and improvement in performance (1.59× on average) over the best mesh and mesh-based custom topologies. An actual layout of a multimedia SoC with the NoC designed using our methodology is presented, which shows that the designed NoC supports the required frequency of operation (close to 900 MHz) without any timing violations. We could design the NoC from input specifications to layout in 4 hours, a process that usually takes several weeks.

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Increasing miniaturization is posing multiple challenges to electronic designers. In the context of Multi-Processor System-onChips (MPSoCs), we focus on the problem of implementing efficient interconnect systems for devices which are ever more densely packed with parallel computing cores. Easily seen that traditional buses can not provide enough bandwidth, a revolutionary path to scalability is provided by packet-switched Network-on-Chips (NoCs), while a more conservative approach dictates the addition of bandwidth-rich components (e.g. crossbars) within the preexisting fabrics. While both alternatives have already been explored, a thorough contrastive analysis is still missing. In this paper, we bring crossbar and NoC designs to the chip layout level in order to highlight the respective strengths and weaknesses in terms of performance, area and power, keeping an eye on future scalability. 1